Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only
Reexamination Certificate
2002-12-13
2004-05-25
Ngo, Julie-Huyen L. (Department: 2871)
Liquid crystal cells, elements and systems
Particular structure
Having significant detail of cell structure only
C349S039000, C349S139000
Reexamination Certificate
active
06741313
ABSTRACT:
This application claims the benefit of Korean Patent Application No. 2001-84259, filed on Dec. 24, 2001 in Korea, which is hereby incorporated by reference for all purposes as if fully set forth herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and more particularly, to an array substrate for In-Plane Switching (IPS) mode liquid crystal display device and fabricating method for the same in order to realize a minute pixel.
2. Discussion of the Related Art
A typical liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite orientation order in alignment resulting from their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by supplying an electric field to the liquid crystal molecules. In other words, as the alignment direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Because incident light is refracted to the orientation of the liquid crystal molecules due to the optical anisotropy of the aligned liquid crystal molecules, image data is displayed.
Currently, active matrix LCDs, in which the thin film transistors and the pixel electrodes are arranged in the form of a matrix, are widely used because of their high resolution and superiority in displaying moving images. An array substrate for the related art in-plane switching (IPS) mode liquid crystal display (LCD) device and the fabricating method for the same will be described hereinafter.
FIG. 1
is a plan view of a pixel of an array substrate for a related art in-plane switching (IPS) mode liquid crystal display (LCD) device. As shown in the figure, a plurality of gate lines
12
and common lines
16
are horizontally formed on an array substrate
10
and they are spaced apart from each other. A plurality of data lines
24
is vertically formed on the array substrate
10
and cross the gate lines
12
and the common lines
16
. The data line
24
defines a pixel “P” by crossing the gate line
12
. A thin film transistor “T” is formed in a cross point of the gate line
12
and the data line
24
. The thin film transistor “T” includes a gate electrode
14
, an active layer
20
, a source electrode
26
and a drain electrode
28
. The active layer
20
, the source electrode
26
and the drain electrode
28
are formed over the gate electrode
14
. The gate electrode
14
communicates with the gate line
12
and the source electrode
26
communicates with the data line
24
. A pixel electrode
30
that communicates with the drain electrode
28
and a common electrode
17
that is parallel with the pixel electrode
30
are formed in the pixel region “P”. The common electrode
17
communicates with the common line
16
. The pixel electrode
30
includes an extension portion
30
a
, a vertical portion
30
b
and a horizontal portion
30
c
. The extension portion
30
a
of the pixel electrode
30
is extended from the drain electrode
28
and the vertical portion
30
b
of the pixel electrode
30
is vertically extended from the extension portion
30
a
. The horizontal portion
30
c
of the pixel electrode
30
is formed over the common line
16
and connected to the vertical portion
30
b
. The common electrode
17
includes a horizontal portion
17
a
and a plurality of vertical portions
17
b
. The plurality of vertical portions
17
b
of the common electrode
17
is arranged in an alternating order with the vertical portion
30
b
of the pixel electrode
30
. The horizontal portion
17
a
of the common electrode
17
connects the plurality of the vertical portion
17
b
into one portion. An auxiliary storage capacitor “C” is formed in the pixel region “P”. The auxiliary storage capacitor “C” uses a portion of the common line
16
as a first storage electrode and the horizontal portion of the pixel electrode
30
c
as a second storage electrode.
FIGS. 2A
to
2
C are cross-sectional views taken along II—II and III—III of
FIG. 1
illustrating a fabrication process according to a fabrication sequence of the related art. In
FIG. 2A
, the gate line
12
of
FIG. 1
including the gate electrode
14
, the common line
16
and the common electrode
17
are formed on the substrate
10
by depositing and patterning conductive metal material such as aluminum (Al), aluminum neodymium (AlNd), chromium (Cr), molybdenum (Mo) or tungsten (W), for example. A gate insulating layer
18
is then formed on the substrate
10
by depositing inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO
2
), for example. The active layer
20
and an ohmic contact layer
22
are formed on the gate insulating layer
18
by depositing and patterning amorphous silicon (a-Si:H) and doped amorphous silicon (n+a-Si:H or p+a-Si:H).
In
FIG. 2B
, the data line
24
, the source electrode
26
, the drain electrode
28
and the pixel electrode
30
are formed on the substrate
10
by depositing and patterning conductive metal material such as aluminum (Al), aluminum neodymium (AlNd), chromium (Cr), molybdenum (Mo) or tungsten (W), for example. The data line
24
defines the pixel region “P” by crossing the gate line
12
and the common line
16
. The source electrode
26
is formed by being extended from the data line
24
and partially overlapped with the active layer
20
. The drain electrode
28
is spaced apart from the source electrode
26
. The pixel electrode
30
comprises the extension portion
30
a
, the vertical portion
30
b
and the horizontal portion
30
c
. The horizontal portion
30
b
of the pixel electrode
30
is formed on the common line
16
. The active layer
20
portion between the source electrode
26
and the drain electrode
28
is exposed by etching the ohmic contact layer
22
between the source electrode
26
and the drain electrode
28
.
In
FIG. 2C
, a passivation layer
32
is formed on the substrate
10
by coating organic insulating material such as benzocyclobutene (BCB), for example, or by depositing inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiO
2
), for example.
FIG. 3
is a circuit diagram of
FIG. 1. A
capacitor communicates with the thin film transistor “T” in series. The capacitor includes a liquid crystal capacitor (C
LC
) and a storage capacitor (C
ST
), which is connected in parallel to the liquid crystal capacitor (C
LC
).
However, if the pixel structure stated above for the in-plane switching (IPS) mode liquid crystal display (LCD) device that drives a minute pixel, an area for the storage capacitor “C” is limited. Moreover, if the area for the storage capacitor “C” is designed to be larger in order to secure a capacitance of the storage capacitor “C”, an aperture ratio of the liquid crystal panel is decreased.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to an array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device and method for fabricating the same that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide the array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device in order to secure enough auxiliary capacitance without enlarging an area of a storage capacitor “C”.
Another advantage of the present invention is to provide a fabricating method for the array substrate for in-plane switching (IPS) mode liquid crystal display (LCD) device in order to secure enough auxiliary capacitance without enlarging an area of a storage capacitor “C”.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description a
Chae Gee-Sung
Kim Ik-Soo
LG. Philips LCD Co. Ltd.
McKenna Long & Aldridge LLP
Ngo Julie-Huyen L.
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