Array substrate for IPS mode liquid crystal display device...

Liquid crystal cells – elements and systems – Particular structure – Having significant detail of cell structure only

Reexamination Certificate

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C349S038000

Reexamination Certificate

active

06791651

ABSTRACT:

The present invention claims the benefit of Korean Patent Application No. 2001-87619, filed in Korea on Dec. 28, 2001, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to an array substrate for an In-Plane Switching (IPS) mode liquid crystal display device and fabricating method for the same.
2. Discussion of the Related Art
Liquid crystal display (LCD) devices commonly make use of optical anisotropy and polarization properties of liquid crystal molecules to produce image data. The liquid crystal molecules have a definite alignment direction resulting from their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by application of an electric field. Accordingly, as the alignment direction of the applied electric field is changed, the alignment of the liquid crystal molecules also changes. Because incident light is refracted by the orientation of the liquid crystal molecules due to their optical anisotropy, image data is displayed. Active matrix liquid crystal display (LCD) devices, in which the thin film transistors and the pixel electrodes are arranged in the form of a matrix, are commonly used because of their high resolution and superiority in displaying moving images. An array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device and a fabrication method for the same will be described hereinafter with reference to figures attached.
FIG. 1
is a plan view of a pixel of an array substrate for a related art in-plane switching (IPS) mode liquid crystal display (LCD) device. In
FIG. 1
, the array substrate for the in-plane switching (IPS) mode liquid crystal display (LCD) device has a plurality of gate lines
12
, common lines
16
and data lines
24
, wherein the gate line
12
and the common line
16
are formed along a horizontal direction and the data line
24
crosses the gate line
12
and the common line
16
, thereby defining a pixel region “P” by crossing the data line
24
. A gate pad electrode
13
is formed at one end of the gate line
12
, and a data pad electrode
25
is formed at one end of the data line
24
. A thin film transistor “T” is formed at a cross point of the gate and data lines
12
and
24
. The thin film transistor “T” includes a gate electrode
14
, an active layer
20
, a source electrode
26
, and a drain electrode
28
. The gate electrode
14
extends from the gate line
12
, and the source electrode
26
is electrically connected to the data line
24
. A pixel electrode
30
and a common electrode
17
are formed within the pixel region “P,” wherein the pixel electrode
30
is electrically connected to the drain electrode
28
. The common electrode
17
is formed parallel with the pixel electrode
30
and is electrically connected to the common line
16
. The pixel electrode
30
includes an extension portion
30
a
, a plurality of vertical portions
30
b
, and a horizontal portion
30
c
. The extension portion
30
a
extends from the drain electrode
28
, the vertical portion
30
b
vertically extends from the extension portion
30
a
, and the extension and vertical portions
30
a
and
30
b
are spaced apart from each other. The horizontal portion
30
c
is disposed over the common line
16
, and electrically interconnects the plurality of vertical portions
30
b
. The common electrode
17
has a plurality of vertical portions
17
b
and a horizontal portion
17
a
. The vertical portions
17
b
vertically extend from the common line
16
and are arranged in an alternating pattern with the vertical portion
30
b
of the pixel electrode
30
. The horizontal portion
17
a
electrically interconnects the plurality of vertical portions
17
b
. The vertical portion
17
b
is spaced apart from the data line
24
. A storage capacitor “C” is formed within the pixel region “P,” and uses a portion of the common line
16
as a first storage electrode and a horizontal portion
30
c
of the pixel electrode
30
as a second electrode. The gate pad electrode
13
electrically contacts a gate pad terminal electrode
30
through a gate pad contact hole
33
. The data pad electrode
25
electrically contacts a data pad terminal electrode
41
through a data pad contact hole
35
. The source electrode
25
, the drain electrode
28
, and the data line
24
are formed to have a single layer using one of molybdenum (Mo) or chromium (Cr). However, metals such as molybdenum (Mo) or chromium (Cr), which are used for the source and drain electrode
26
and
28
, have a high electric resistance and are not suitable for large-sized liquid crystal display panels.
FIGS. 2A
to
2
D are cross-sectional views taken along II—II, III—III, IV—IV and V—V of FIG.
1
and illustrate a fabrication sequence of an array substrate according to the related art. In
FIG. 2A
, the gate line
12
, the gate pad electrode
13
, and the common line
16
are formed on the substrate
10
by depositing and patterning a conductive metal material, such as aluminum (Al) and an aluminum alloy. The gate electrode
14
is a part of the gate line
12
, and the common line
16
is spaced apart from the gate line
12
. The plurality of vertical portions
17
b
of the common electrode
17
vertically extend from the common line
16
, and the horizontal portion
17
a
(not shown) of the common electrode
17
electrically interconnects the plurality of vertical portions
17
b
. The gate electrode
14
, the gate line
12
, and the gate pad electrode
13
have a dual-layer structure. The dual-layer structure of the gate line
12
and the gate electrode
14
includes aluminum (Al). For example, aluminum (Al) is used for a first metal layer and molybdenum (Mo) or chromium (Cr) is used for a second metal layer. Then, a gate insulating layer
18
is formed on the substrate
10
using silicon nitride (SiNx). A first pattern
20
, a second pattern
21
, and a third pattern
22
are formed by simultaneously depositing and patterning amorphous silicon (a-Si:H) and impurities doped amorphous silicon (n
+
a-Si:H) on the gate insulating layer
18
. The first pattern
20
is disposed within an active region “A” over the gate electrode
14
, the second pattern
21
over the common line
16
and the third pattern within a data pad region “D.” The second pattern
21
and the third pattern
22
improve a contact property of a metal layer that will be formed thereon in a later process. An amorphous silicon (a-Si:H) layer of the first pattern
20
is commonly referred to as an active layer
20
a
, and an impurities doped amorphous silicon (n
+
a-Si:H or p
+
a-Si:H) of the first pattern
20
is commonly referred to as an ohmic contact layer
20
b.
In
FIG. 2B
, the data line
24
, the source electrode
26
, the drain electrode
28
, and the pixel electrode
30
b
and
30
c
are formed by depositing and patterning one of chromium (Cr) and molybdenum (Mo) on the substrate
10
. The data line
24
defines the pixel region “P” by crossing the gate line
12
. The source electrode
26
extends from the data line
24
and electrically contacts the ohmic contact layer
20
b
, and the drain electrode
28
is spaced apart from the source electrode
26
. The pixel electrode
30
includes the extension portion
30
a
(not shown), the plurality of vertical portions
30
b
, and the horizontal portion
30
c
. The data pad electrode
25
is formed at one end of the data line
24
.
In
FIG. 2C
, a passivation layer
32
is formed by depositing silicon nitride (SiNx) on the substrate
10
. A gate pad contact hole
33
is formed to expose a portion of the gate pad electrode
13
, and a data pad contact hole
35
is formed to expose a portion of the data pad electrode
25
by patterning the passivation layer
32
.
In
FIG. 2D
, both the gate pad terminal electrode
39
is formed with the gate pad electrode
13
and the data pad terminal electrode
41
is formed with the data pad electrode
25
by depositing and patte

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