Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Having diverse electrical device
Reexamination Certificate
2002-02-05
2004-02-10
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Making device or circuit emissive of nonelectrical signal
Having diverse electrical device
C438S149000, C438S073000, C257S072000, C257S748000
Reexamination Certificate
active
06689629
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an array substrate for display, a method of manufacturing the array substrate for display and a display device using the array substrate for display.
A display device using a thin film transistor (TFT) array has been frequently used owing to low power consumption and capability of downsizing the display device. The thin film transistor array is manufactured by forming thin film transistors, each being composed of electrodes such as a gate electrode, a source electrode and a drain electrode, wirings such as scan lines and signal lines connected with the above-mentioned electrodes, and pixel electrodes on an insulating substrate.
In recent years, a higher operating speed, a higher resolution and a larger size have been required for the display device described above in many cases. A high speed and a high density have been required for each constituent component of the array for display, which forms a display device. Particularly, in order to operate the thin film transistor array at a high speed, it is preferable to use low-resistance aluminum (Al) for the wirings such as the scan lines and the signal lines since delay in gate pulses can be reduced and a writing speed to the thin film transistor can be increased.
Incidentally, aluminum tends to be easily oxidized in spite of its low resistance. Therefore, in many cases, wiring using aluminum is constituted as a two-layer structure, in which aluminum is used as a lower conductive material, and a material harder to be oxidized than aluminum such as chromium, tantalum, titanium or molybdenum is used as an upper conductive material.
FIG. 11
is a view schematically showing a state where wiring
2
is deposited on an insulating substrate
1
. A lower conductive material film
2
a
is deposited on an insulating substrate
1
made of such as glass, and an upper conductive material film
2
b
is deposited on the lower conductive material film
2
a
. Each of these films
2
a
and
2
b
is patterned by, for example, a proper etching process so as to have tapered ends.
In order to form a tapered shape shown in
FIG. 11
, an etching rate for the upper conductive material is required to be increased. In order to form the tapered shape shown in
FIG. 11
, various methods have been proposed up to now. For example, in the gazette of Japanese Patent Laid-Open No. Hei 10 (1998)-90706, a method has been proposed, in which dummy connection pads are provided on sides opposite to scan line connection pads and signal line connection pads, respectively. According to this method, over etching due to an etchant that will be relatively increased by lowering wiring density at ends of the substrate is prevented. Thus, undercut of a lower conductive material
3
is prevented, and an interlayer short circuit is prevented by imparting a proper tapered shape to the wiring
2
.
However, though this method enables evenness of etching at the ends of the thin film transistor array substrate to be improved, the method cannot effectively prevent the undercut of the signal lines in a region where the wiring density is apt to be lowered from ends of the pixel electrodes to the connection pads, for example, in a portion where drawing wiring is formed.
Moreover, in the gazette of Japanese Patent Laid-Open No. Hei 10 (1998)-240150, disclosed is a method of forming a tapered shape at an angle ranging from 20 degrees to 70 degrees on wiring constituted of two layers, in which a pad formed of aluminum and metal such as molybdenum formed on the aluminum is subjected to wet etching. According to this method, a specified tapered shape can be imparted to the wiring formed of a conductive film of a two-layer structure by the wet etching. However, the method never discloses a method of evenly etching a substrate region while maintaining a selection ratio thereof even in the substrate region where the wiring density is lowered.
FIGS. 12A and 12B
are enlarged schematic views for explaining a patterning process using a conventionally used wet process in order to impart the above-described tapered shape to the wiring. As shown in
FIG. 12A
, the lower conductive material
3
and an upper conductive material
4
are deposited on the insulating substrate
1
by a method such as physical vapor deposition.
FIG. 12A
shows that a photoresist film
5
is coated on a film of the upper conductive material
4
and is patterned in a desired shape. The respective films are etched by an etchant such as a solution of phosphoric acid, nitric acid, acetic acid or mixtures thereof, and desired tapered shapes are formed thereon.
FIG. 12B
is a view for explaining an electrochemical process generated as each film is being etched when the wiring constituted of the upper conductive material
4
and the lower conductive material
3
is subjected to wet etching. In
FIG. 12B
, an internal layer portion of the upper conductive material
4
coated with the photoresist film
5
is not dissolved. However, at the end of the photoresist film
5
, the upper conductive material
4
is dissolved by the etchant. When the wiring is formed by the wet etching, the upper conductive material
4
protected by the photoresist film
5
is further dissolved in a lateral direction from the end of the photoresist film
5
to turn into positive ions, and electrons emitted as a result are supplied to the lower conductive material
3
. Thus, the upper conductive material
4
serves as an anode. In this connection, the lower conductive material
3
comes to serve as a cathode. Accordingly, an electrochemical cell is formed. Here, when the etching rate for the upper conductive material
4
is increased to form a required tapered shape, the density of the electrons generated by dissolving the upper conductive material
4
and flowing to the lower conductive material
3
is increased accompanied with an increase of a dissolution rate of the upper conductive material
4
.
FIG. 12B
schematically shows currents I flowing from the upper conductive material
4
to the lower conductive material
3
.
As the etching rate is increased, the density of the current flowing to an area of the upper conductive material
4
, which is exposed to the etchant, exceeds a current density causing passivity of the upper conductive material
4
. In such a case, the upper conductive material
4
is passivated not to be dissolved by the etchant, and only the lower conductive material
3
is dissolved accompanied with the progress of the etching, resulting in the occurrence of the undercut. When such undercut occurs, the wiring, for example, the gate wiring cannot be sufficiently coated with an insulating film in some cases, thus causing inconvenience such as an interlayer short circuit, resulting in lowering a yield of the display device.
SUMMARY OF THE INVENTION
The present invention was made with the foregoing problems in mind. An object of the present invention is to provide an array substrate for display, a method of manufacturing an array substrate for display and a display device using the array substrate for display, which are capable of being etched at a sufficiently high etching rate and a sufficient selection ratio, eliminating undercut, and providing a large-sized and high-resolution display device.
The foregoing object of the present invention is achieved by providing the array substrate for display, the method of manufacturing an array substrate for display and the display device using the array substrate for display of the present invention.
Specifically, according to the present invention, provided is an array substrate for display, comprising: a thin film transistor array formed on an insulating substrate; a plurality of wirings arranged on the insulating substrate; connection pads arranged on unilateral ends of the wirings and respectively connected with the wirings; pixel electrodes, and dummy conductive patterns arranged between the ends of the connection pads and ends of the pixel electrodes. The dummy conductive patterns can occupy 30 area % or more. In the present inventi
Arai Toshiaki
Makita Atsuya
Tsujimura Takatoshi
Everhart Caridad
Townsend Tiffany L.
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