Array substrate and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material

Reexamination Certificate

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Details

C257S072000, C257SE21414, C349S048000, C349S049000, C349S050000, C345S090000, C345S091000, C345S092000

Reexamination Certificate

active

07910925

ABSTRACT:
The present invention provides an array substrate and a method for manufacturing the same. The array substrate comprises a substrate and a plurality of gate lines parallel to each other and a plurality of data lines parallel to each other formed on the substrate, the gate lines intersecting the data lines to define a plurality of pixel region arranged in a matrix, each pixel region comprising a thin film transistor, a pixel electrode and a thin film diode. With respect to each pixel region in a row, the pixel electrode is connected with the gate line in the present row through the thin film transistor and is connected with the gate line in a previous row through the thin film diode.

REFERENCES:
patent: 5528395 (1996-06-01), So
patent: 6392254 (2002-05-01), Liu et al.
patent: 2001/0054711 (2001-12-01), Numao
patent: 2004/0119901 (2004-06-01), Kang
patent: 2004/0257513 (2004-12-01), Chin et al.
patent: 62135814 (1987-06-01), None
patent: 2003-188384 (2003-07-01), None
patent: 2003-195260 (2003-07-01), None
patent: 1995-29822 (1995-11-01), None
English abstract of KR 1995-29822 dated Nov. 24, 1995.
Patent Abstracts of Japan and English translation of JP 2003-195260 dated Jul. 9, 2003.
Patent Abstracts of Japan and English translation of JP 2003-188384 dated Jul. 4, 2003.

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