Array substrate and method of fabricating the same

Details Array substrate and method of fabricating the same Array substrate and method of fabricating the same

2011-08-02

2011-08-02

Cao, Phat (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular signal path connections

C257S059000, C257S072000, C257S088000, C257S204000, C257S365000, C257S366000, C257S412000, C257S524000, C257SE33003, C257SE33004, C257SE33053, C257SE27060, C257SE27081, C257SE27111

Reexamination Certificate

active

07989850

ABSTRACT:
An array substrate includes first and second gate electrodes on a substrate; a gate insulating layer on the first and second gate electrodes; first and second active layers on the gate insulating layer; an interlayer insulating layer on the first and second active layers; first to fourth ohmic contact layers respectively contacting both sides of the first active layer and both sides of the second active layer; first and second source electrodes and first and second drain electrodes respectively on the first, third, second and fourth ohmic contact layers; a data line connected to the first source electrode; a first passivation layer connected to the first gate electrode; a power line; one end and the other end of a connection electrode respectively connected to the first drain electrode and the second gate electrode; a second passivation layer; and a pixel electrode-connected to the second drain electrode.

REFERENCES:
patent: 2008/0002125 (2008-01-01), Kim
patent: 10-2003-0015618 (2003-02-01), None
patent: 10-2005-0003249 (2005-01-01), None
patent: 10-2008-0053698 (2008-06-01), None
patent: 10-2008-0059827 (2008-07-01), None

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