Array structure for assisted-charge memory devices

Details Array structure for assisted-charge memory devices Array structure for assisted-charge memory devices

2007-04-24

2007-04-24

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

C365S185280

Reexamination Certificate

active

11327561

ABSTRACT:
An Assisted Charge (AC) Memory cell comprises a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can comprise a trapping structure. The trapping structure can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the structure. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency.

REFERENCES:
patent: 5774400 (1998-06-01), Lancaster et al.
patent: 6011725 (2000-01-01), Eitan
patent: 2006/0146603 (2006-07-01), Kuo et al.

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