Array split across three-dimensional interconnected chips

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C365S072000

Reexamination Certificate

active

07420832

ABSTRACT:
A semiconductor storage array has a first array portion on a first plane of circuitry and a second array portion on a second plane of circuitry. A composite bit line and/or a composite word line is divided and arranged to have a first portion on the first array portion and a second portion on the second array portion. The two portions of the composite word line or the composite bit line are on different planes of circuitry, and three-dimensional interconnections connect proximal ends of the word line portions, or proximal ends of the bit line portions. A word line driver drives the word line portions in parallel. A bit line driver drives the bit line portions in parallel. Signal propagation times down the composite word or bit lines are significantly less than signal propagation times down corresponding undivided word or bit lines.

REFERENCES:
patent: 5818748 (1998-10-01), Bertin et al.
patent: 6291858 (2001-09-01), Ma et al.
patent: 6477077 (2002-11-01), Okazawa
patent: 6738279 (2004-05-01), Kablanian
patent: 2004/0057276 (2004-03-01), Nejad et al.
patent: 2004/0124466 (2004-07-01), Walker et al.

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