Electrical resistors – With mounting or supporting means – Plural resistors
Reexamination Certificate
2002-04-30
2003-06-10
Easthom, Karl D. (Department: 2832)
Electrical resistors
With mounting or supporting means
Plural resistors
C338S203000, C338S322000, C338S325000, C338S260000
Reexamination Certificate
active
06577225
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention generally relates to resistors for electronics. Specifically, the invention is a group of resistors mounted in a high density network or array package.
2. Description of the Related Art
Resistor networks are commonly used to terminate high speed digital signal lines to minimize unwanted reflections back through the transmission structure which is typically a printed circuit board. In most applications, the terminations are made by placing a resistor with a resistance matching the impedance of the transmission line, at the end of the transmission line. One end of the resistor is connected to a common termination voltage and the other end is connected to the signal line. For these applications, a bussed resistor network is a convenient solution, since one end of the termination is common to all signal lines.
The previous resistor network designs include surface mount, through hole SIP and DIP versions and chip resistor arrays.
Despite the advantages of each type of prior art resistor network, there is still difficulty in economically manufacturing resistors with a high density of interconnects per unit area. In particular, providing electrical connections only on the periphery of the resistor network causes the electrical leads to be tightly spaced on the edge of the device, while the area in the interior of the device is unused for electrical interconnections.
Therefore, there is a current unmet and heretofore long felt need for a resistor network with higher density that can be manufactured at low cost.
SUMMARY
It is a feature of the invention to provide an array resistor network that has a high density of resistors per unit area.
It is a feature of the invention to provide an array resistor network that includes a substrate that has a first and a second surface and first, second, third and fourth edges. Several apertures extend through the substrate between the first and second surfaces. Several recesses are located in the first and second edges. Several resistors are disposed on the first surface. Each resistor is located between the recess and the apertures. Several first conductors are connected to a first end of the resistors. The first conductors are located on the first surface and extend through the aperture onto the second surface. Several second conductors are connected to a second end of the resistors. The second conductors are located on the first surface and extend through the recess onto the second surface.
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Bourgeois Mark P.
CTS Corporation
Easthom Karl D.
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