Array processor and control method thereof

Details Array processor and control method thereof Array processor and control method thereof

1988-06-14

1990-02-27

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1516, G06F 1500

Patent

active

049051431

ABSTRACT:
An array processor comprising multiplexers, plural processing elements connected through the multiplexers in the form of a ring and a control unit for controlling the multiplexers and the processing elements. Each of the processing elements is connected to an input vector data bus via the multiplexer and directly to an I/O data bus, so that two types of input vector data are inputted to the processing element simultaneously. Flags indicating a position of respective vector data are added to each one of input vector data, series composed of a combination of plural types of input vector data series. The processing element judges a processing status of the processing element to control a selection of the input vector data bus or the transfer path, data transfer between the processing elements, or data input/output to/from the I/O bus, so that the overall array processor executes autonomous control of all the combinations of the vector data of the two types of input vector data series. The array processor realizes parallel processing of pattern matching computation based upon dynamic time warping with a high efficiency and thus realizes a highefficiency utilization of hardware resources including processing elements and network.

REFERENCES:
patent: 3287703 (1966-11-01), Slotnick
patent: 3544973 (1970-12-01), Borck
patent: 3582899 (1971-06-01), Semmelhaak
patent: 3970993 (1976-07-01), Finnila
patent: 4065808 (1977-12-01), Schomberg et al.
patent: 4270169 (1981-05-01), Reddaway
patent: 4270170 (1981-05-01), Hunt et al.
patent: 4314349 (1982-02-01), Batcher
patent: 4334305 (1982-06-01), Giradi
patent: 4380046 (1983-04-01), Fung
patent: 4384273 (1983-05-01), Ackland et al.
patent: 4428048 (1984-01-01), Berlin, Jr.
patent: 4466064 (1984-08-01), Martin
patent: 4467422 (1984-08-01), Hunt
patent: 4509187 (1985-04-01), Ackland et al.
patent: 4533993 (1985-08-01), McCanny et al.
patent: 4541048 (1985-09-01), Propster et al.
patent: 4628481 (1986-12-01), Reddaway
patent: 4739474 (1988-04-01), Holsztynski
patent: 4739476 (1988-04-01), Fiduccia
patent: 4783738 (1988-11-01), Li et al.
Ackland et al, "Array Configurations for Dynamic Time Warping," IEEE Conference on Acoustics Speech & Signal Proc. pp. 119-127, Feb./1984.
D. J. Burr et al, A High Speed Array Computer for Dynamic Time Warping, Bell Laboratories, N.J., IEEE 1981 pp. 471-474.
Bryan Ackland et al, An Integrated Multiprocessing Array for Time Warp Pattern Matching, Bell Laboratories, N.J., IEEE 1981 pp. 197-203.
N. H. E. Weste et al, Speech Processing, IEEE 1982, Bell laboratories in New Jersey, pp. 274-275.
VLSI Structures for Speech Analysis and Pattern Recognition, IEEE Proceedings Jun. 14-17, 1982, pp. 692-697.

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