Boots – shoes – and leggings
Patent
1991-01-31
1992-03-10
Shaw, Gareth D.
Boots, shoes, and leggings
364DIG1, 3642319, 3642419, 364260, G06F 1580
Patent
active
050955276
ABSTRACT:
A novel array processor is provided with a plurality of local memories in each data processing element and allows these local memories to be accessed simultaneously, so that a plurality of local memories provided for each data processing element can simultaneously be accessed. The array processor is also has one local memory which is provided with a plurality of output ports for each data processing element, so that all the output ports can simultaneously be accessed, permitting the local memory unit to be accessed simultaneously through a plurality of output ports. The array processor of the present invention decreases the number of memory accesses in each data processing element, with the cumulative effect of achieving a faster speed for the entire data processing system.
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patent: 4107773 (1978-08-01), Gilbreath et al.
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patent: 4905143 (1990-02-01), Takahashi et al.
patent: 4907148 (1990-03-01), Morton
patent: 4922418 (1990-05-01), Dolecek
Kondo et al., "An LSI Adaptive Array Processor", IEEE Journal of Solid-State Circuits, vol. SC-18, No. 2, Apr. 1983, pp. 147-156.
"Geometric Arithmetic Parallel Processor" NCR 45CG72, National Cash Register, Inc., U.S.A. (1984).
Terane Hideyuki
Uramoto Shin-ichi
Loomis John
Mitsubishi Denki & Kabushiki Kaisha
Shaw Gareth D.
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