Array-processed stacked semiconductor packages

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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C438S127000, C257SE23001

Reexamination Certificate

active

07892889

ABSTRACT:
One embodiment of the invention is a semiconductor system (1400) of arrays (1401, 1402, etc.) of packaged devices. Each array includes a sheet-like substrate (1411, 1412, etc.) made of insulating material integral with conductive horizontal lines and vertical vias, and terminals on the surfaces. Semiconductor components, which may include more than one active or passive chips, or chips of different sizes, are attached to the substrate; the electrical connections may include flip-chip, wire bond, or combination techniques. Encapsulation compound (1412, 1422, etc.), which adheres to the substrate, embeds the connected components. Metal posts (1431, 1432, etc.) traverse the encapsulation compound vertically, connecting the substrate vias with pads on the encapsulation surface. The pads are covered with solder bodies used to connect to the next-level device array so that a 3-dimensional system of packaged devices is formed.

REFERENCES:
patent: 6268662 (2001-07-01), Test et al.
patent: 6815254 (2004-11-01), Mistry et al.
patent: 2005/0184377 (2005-08-01), Takeuchi et al.
patent: 2007/0262436 (2007-11-01), Kweon et al.
patent: 2007/0262470 (2007-11-01), Ichiryu et al.
patent: 2008/0023805 (2008-01-01), Howard et al.

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