1996-10-18
1999-03-30
Harrell, Robert B.
G06F 900
Patent
active
058899855
ABSTRACT:
An array prefetch system improves processor performance by automatically tuning a statically compiled and compacted loop program at run-time to accommodate variations in latency of memory read operations. Using the array prefetch system, the processor, while awaiting completion of a data access, continues to generate requests for subsequent iterations rather than fully halting execution until a read access is finished.
REFERENCES:
patent: 4128880 (1978-12-01), Cray, Jr.
patent: 5201058 (1993-04-01), Kinoshita et al.
Babaian Boris A.
Gorokhov Valeri G.
Gruzdov Feodor A.
Sakhin Yuli Kh.
Volkonski Vladimir Yu.
Elbrus International
Harrell Robert B.
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