Array of thin film transistors without a step region at intersec

Details Array of thin film transistors without a step region at intersec Array of thin film transistors without a step region at intersec

1996-03-19

1998-10-27

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

257 72, 359 59, H01L 2904, H01L 31036, G02F 11343

Patent

active

058280839

ABSTRACT:
An array of thin film transistors, which minimizes a stepped part in a cross-over region between a gate bus line and a source bus line. Each thin film transistor in the array has associated therewith a structure which includes: a gate bus electrode located on a substrate surface, a first insulating layer covering the gate bus electrode and the substrate surface, a non-monocrystalline semiconductor layer on the first insulating layer above the gate bus electrode, a second insulating layer on the non-monocrystalline semiconductor layer above the gate bus electrode, an n+ monocrystalline layer on the second insulating layer and the non-monocrystalline layer, and a source bus electrode on the n+ monocrystalline layer. A bus line structure in the array is fabricated by the process described above. In the bus line structure, each of the non-monocrystalline semiconductor layer, the second insulating layer, and the n+ non-monocrystalline semiconductor layer is patterned in the same direction as the source bus line. Additionally, the second insulating film is made wider than the source bus line and both the non-monocrystalline semiconductor layer and the n+ non-monocrystalline semiconductor layer are made wider than the second insulating layer.

REFERENCES:
patent: 4816885 (1989-03-01), Yoshida et al.
patent: 4997262 (1991-03-01), Sakono et al.
patent: 5021850 (1991-06-01), Tanaka et al.

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