Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-01-19
2001-01-30
Carroll, J. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S635000, C257S734000
Reexamination Certificate
active
06180994
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an array of antifuses and, more particularly, to an array of sidewall-contacted antifuses having diffused bit lines.
2. Description of the Related Art
Unlike a fuse which, when programmed, changes from a low-resistance to a high-resistance device to block a current from flowing through the device, an antifuse is a device which, when programmed, changes from a high-resistance to a low-resistance device to allow a current to flow through the device.
FIG. 1
shows a plan drawing that illustrates a portion of a conventional antifuse array
100
.
FIG. 2
shows a cross-sectional drawing taken along line
2
—
2
of FIG.
1
. As shown in
FIGS. 1 and 2
, array
100
includes a series of polysilicon (poly) bit lines BL
1
-BLm which are formed on a first layer of oxide
110
. As further shown, each bit line BL has a series of projections P
1
-Pn which, in turn, each have an end sidewall
112
.
In addition, array
100
further includes a second layer of oxide
114
which is formed over bit lines BL
1
-BLm and oxide layer
110
, but which is not formed on the end sidewalls
112
and the regions of oxide layer
110
that lie between opposing end sidewalls
112
.
Array
100
also includes a series of word lines WL
1
-WLn which are formed on oxide layers
110
and
114
and the end sidewalls
112
such that a word line WL is connected to all of the end sidewalls
112
in a row of end sidewalls. Each word line WL, in turn, includes a dielectric layer DL and an overlying poly layer PL.
The resulting structure forms a plurality of sidewall-contacted antifuses
116
in that an antifuse
116
is formed each time a word line WL contacts the end sidewall
112
of a bit line BL.
In operation, each antifuse
116
is used to store one of two logic values depending on whether or not the dielectric associated with the antifuse is intact. For example, antifuse A represents a first logic state when the dielectric of word line WL
1
formed over end sidewall
112
of bit line BL
1
is intact in that no current can flow from word line WL
1
to bit line BL
1
(or in the opposite direction). Thus, when normal operating voltages are applied to word line WL
1
, only a fraction of the voltage is coupled to bit line BL
1
.
On the other hand, antifuse A represents a second logic state when the dielectric of word line WL
1
formed over end sidewall
112
of bit line BL
1
has been broken down and thus, is no longer intact, in that current can now flow from word line WL
1
to bit line BL
1
(or in the opposite direction). Thus, when normal operating voltages are applied to word line WL
1
, substantially all of the voltage is present on bit line BL
1
.
The dielectric region of a word line that forms an antifuse is typically broken down by establishing a strong electric field across the dielectric region. This programming of the antifuse changes the logic state of the antifuse from the first logic state to the second logic state.
For example, with antifuse A, the dielectric of word line WL
1
formed over end sidewall
112
of bit line BL
1
breaks down when a 10.6V pulse is applied to word line WL
1
while bit line BL
1
is grounded.
One of the problems with antifuse array
100
is that antifuses
116
are sensitive to masking alignment errors that occur during fabrication.
FIGS. 3A-3F
show a series of plan views that illustrate the fabrication of antifuse array
100
. (See also Chen et al., A Sublithographic Antifuse Structure for Field Programmable Gate Array Applications,
IEEE Electron Device Letters,
Vol. 13, No. 1, January 1992.)
As shown in
FIG. 3A
, antifuse array
100
is fabricated by depositing a layer of first polysilicon (poly-1)
310
over a layer of oxide
312
. After this, poly-1 layer
310
is masked and etched to form a poly structure
314
which includes a first strip
316
, a second strip
318
, and a plurality of connecting strips
320
that connect the first and second strips
316
and
318
together.
Following this, poly-1 layer
310
is again masked and etched to reduce the widths W of connecting strips
320
to a dimension which is less than the minimum dimension that can be photolithographically obtained by the fabrication process.
Following this, as shown in
FIG. 3B
, a thick layer of oxide
322
is formed over strips
316
,
318
, and
320
, and the exposed portions of oxide layer
312
. Next, a mask
324
is formed and patterned on oxide layer
322
to expose the regions of oxide layer
322
that are formed over the center portions of connecting strips
320
. After this, the unmasked areas of oxide layer
322
and the underlying portions of strips
320
are etched to form bit lines BL
1
-BLm.
However, as shown in
FIG. 3C
, if mask
324
is vertically misaligned, then the etch will fail to form bit lines BL
1
-BLm. Instead, the etch will leave connecting strips
320
partially or fully intact, depending on the extent of the misalignment.
As shown in
FIG. 3D
, if mask
324
is properly aligned, the next step following the last etch is to form a layer of dielectric material
326
on the top and sidewall surfaces of oxide layer
322
, the end sidewalls of bit lines BL
1
-BLm, and a top surface of oxide layer
312
.
Next, a layer of second polysilicon (poly-2)
328
is formed over dielectric layer
326
. Following this, a mask
330
is formed and patterned over poly-2 layer
328
. The unmasked areas of poly-2 layer
328
and the underlying areas of dielectric layer
326
are then etched to form word lines WL
1
-WLn as shown in FIG.
3
E.
However, as shown in
FIG. 3F
, if mask
330
is vertically misaligned, then the etch will fail to form word lines WL
1
-WLn over connecting strips
320
. Thus, alignment errors during the placement of masks
324
and
330
can result in the formation of nonfunctioning antifuses.
As a result, there is a need for an antifuse array which is less sensitive to masking alignment errors.
SUMMARY OF THE INVENTION
Conventionally, the method for forming an array of sidewall-contacted antifuses is sensitive to masking alignment errors that occur during the fabrication of the array. This sensitivity can lead to lower than desired manufacturing yields. The present invention provides an array of sidewall-contacted antifuses which is less sensitive to masking alignment errors, thereby increasing the manufacturing yields.
In accordance with the present invention, an antifuse array, which is formed on a semiconductor material of a first conductivity type, includes a plurality of spaced-apart bit lines of a second conductivity type which are formed in the semiconductor material.
The array also includes a layer of insulation material which is formed on the semiconductor material over the bit lines. The layer of insulation material has a plurality of openings, which are arranged in rows and columns, that expose a plurality of bit line regions in each bit line.
The array of the present invention further includes a plurality of spaced-apart contacts which are formed on the bit line regions such that each contact is connected to an exposed bit line region. In addition, a layer of isolation material is formed over the layer of insulation material and the contacts such that each contact has an exposed region.
The array additionally includes a plurality of word lines which are formed on the isolation material and the contacts so that a word line is formed on the exposed region of each contact in a row of contacts. Each word line includes a layer of dielectric material and an overlying layer of conductive material.
The present invention also includes a segmented antifuse array which is formed on a semiconductor material of a first conductivity type. The array includes a plurality of sub-arrays which each have a plurality of spaced-apart bit lines of a second conductivity type that are formed in the semiconductor material.
Each sub-array also includes a layer of insulation material which is formed on the semiconductor material over the bit lines. The layer of insulation material has a plurality
Bergemont Albert
Kalnitsky Alexander
Carroll J.
Limbach & Limbach L.L.P.
National Semiconductor Corporation
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