Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-04-14
2004-12-14
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185140
Reexamination Certificate
active
06831863
ABSTRACT:
BACKGROUND OF THE PRESENT INVENTION
1. Field of the Present Invention
The present invention relates to a semiconductor memory device, and more particularly to an array of flash memory cells, in which a unit cell includes a single transistor and to methods for programming and erasing the same.
2. Discussion of the Related Art
An ideal memory element allows for easy programming (writing), easy erasing, and retains a memory state even if power is removed, i.e., is nonvolatile. Nonvolatile semiconductor memories (NVSM) are classified into two types—a floating gate type and a metal insulator semiconductor (MIS) type. The MIS type also may have two or more kinds of stacked dielectric films.
The floating gate type memory uses a potential well to implement memory functions. ETOX (EPROM Tunnel Oxide) structure, which has recently been the most applicable technology for the flash EEPROM (Electrically Erasable Read Only Memory), is typical of the floating gate type. The floating gate type structure can be used to implement a memory cell using a single transistor.
On the other hand, the MIS type memory function uses traps formed in a dielectric film bulk, a boundary layer between two dielectric films, or a boundary layer between a dielectric film and a semiconductor. The MONOS/SONOS (Metal/Poly Silicon Oxide Nitride Oxide Semiconductor) structure, which is used as a full-featured EEPROM, is typical.
To execute the program and erase operations in these memory cells, it is essential that selection transistors be included in addition to the transistors of MONOS/SONOS structure. In other words, each memory cell must include at least two transistors.
The array of conventional flash memory cells and the methods for programming and erasing the same are explained in detail by referring to the accompanying drawings
FIGS. 1-2B
. As seen in
FIG. 1
, a unit cell of the conventional flash memory cells includes two transistors.
FIG. 2A
shows an array of conventional flash memory cells using the cell in
FIG. 1
as the unit cell, and bias conditions for programming the cells.
FIG. 2B
shows the array of conventional flash memory cells using the cell in
FIG. 1
as a unit cell and the bias conditions for erasing the cells.
As seen, the array of conventional flash memory cells is constructed by arranging unit cells in a form of matrix. Each cell includes two transistors—a memory transistor having a MONOS/SONOS structure and a selection transistor for determining whether the cell is selected or not.
A plurality of word lines are constructed in a direction so that the gates memory transistors arranged in a row are commonly connected.
A plurality of word selection lines are constructed in a direction parallel to the word lines so that the gates of selection transistors arranged in a row are commonly connected.
A plurality of bit lines are constructed in a direction perpendicular to the word lines so that the drains of memory transistors arranged in a column are commonly connected.
A plurality of bit selection lines are constructed in a direction parallel to the bit lines so that the drains of selection transistors arranged in a column are commonly connected.
As mentioned above, the conventional unit cell includes a memory transistor having the MONOS/SONOS structure and a selection transistor. A cell is selected by selecting the selection transistor, and program and erase operations are performed on the associated memory transistor.
As shown in
FIG. 1
, the memory transistor has an ONO (Oxide Nitride Oxide) structure including a first oxide film
11
, a nitride film
12
, and a second oxide film
13
sequentially stacked on a portion of a semiconductor substrate
10
. A first gate electrode 15
a
is formed on the oxide film
13
.
The selection transistor includes a gate oxide film
14
and a second gate electrode
15
b
formed on the gate oxide film
14
. The gate oxide film
14
of the selection transistor is thicker than the first and second oxide films
11
and
13
so that a portion of the selection transistor is isolated from the first gate electrode
15
a.
A common source region
16
a
is formed in a portion of the semiconductor substrate
10
between the memory transistor and the selection transistor. Drain regions
16
b
are formed in portions of the semiconductor substrate
10
at the outside of the memory and selection transistors.
In the conventional flash memory cell, programming is accomplished by applying a high positive voltage to the first gate electrode
15
a
. When the high voltage is so applied, electrons from the semiconductor substrate
10
tunnel through the first oxide film
11
and are injected into the nitride film
12
. Thus, the first oxide film
11
is called a tunneling oxide.
The second oxide film
13
prevents electrons injected into the nitride film
12
from leaking into the first gate electrode
15
a
. The second oxide film
13
also prevents electrons from being injected from the first gate electrode
15
a
into the nitride film
12
. Thus, the second oxide film
13
is called a blocking oxide.
Since the program operation uses traps in the boundary layer between the nitride film
12
and the second oxide film
13
, electrons should be injected into or emitted from the entire region of a substrate channel to perform the program and erase operations.
When performing a programming operation, the array of cells is biased in a certain manner. The programming bias condition for the array of conventional flash memory cells is explained as follows.
Referring to
FIG. 2A
, a unit cell, among the plurality of flash memory cells, is selected for programming. Thereafter, a voltage Vp is applied to the word line connected to the gate of the selected memory transistor. Vp is also applied to the word selection line connected to the gate of the selection transistor of the selected cell. Due to the arrangement, the gates of memory transistors and selection transistors of other cells in the same row are also applied with the same Vp voltage.
However, a ground voltage is applied to the word lines of the non-selected rows. Also, the word selection lines of the non-selected rows have their voltages left floating.
For the bit line connected to a drain of the selected memory transistor, the ground voltage is applied. However, for the non-selected bit lines, a voltage Vi is applied. Similarly, for the bit selection line connected to the drain of the selected selection transistor, voltage is left floating, while the non-selected bit selections lines have ground voltages applied.
Finally, ground voltage is also applied to the well (semiconductor substrate) at the lower portion of all the cells regardless of whether that cell is selected or not. The aforementioned bias conditions are simultaneously applied.
Table 1 describes the bias conditions for the programming operation in a table form.
TABLE 1
word
bit
selection
selection
word line
line
bit line
line
well
Selected
Vp
Vp
Ground
Float
Ground
Not
Ground
Float
Vi
Ground
Ground
selected
Note that multiple cells maybe selected at a time for programming, such as a byte at a time.
When performing an erasing operation, the array of cells is differently biased from the programming operation. The erasing bias condition for the array of conventional flash memory cells is explained as follows.
Referring to
FIG. 2B
, a unit cell is selected for erasing. Thereafter, the ground voltage is applied to the word line connected to the gate of the selected memory transistor. Also, Vp is applied to the word selection line connected to the gate of the selection transistor of the selected cell.
However, for the non-selected word lines, voltage Vp is applied, while the word selection lines are left floating.
For the bit line connected to a drain of the selected memory transistor, the ground voltage is applied. However, for the non-selected bit lines, a voltage Vi is applied. Similarly, for the bit selection line connected to the drain of the selected selection transistor, voltage is floating, while the non-selected bit selection lines have ground voltages applied.
Choi Jae Seung
Yi Sang Bae
Hyundai Electronics Industries Co,. Ltd.
Le Thong Q.
LandOfFree
Array of flash memory cells and data program and erase... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Array of flash memory cells and data program and erase..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Array of flash memory cells and data program and erase... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3310552