Array multiplier operating in one's complement format

Details Array multiplier operating in one's complement format Array multiplier operating in one's complement format

1981-03-10

1984-11-20

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

044843011

ABSTRACT:
A method and apparatus for performing a two's complement, single or double precision digital multiply, whereby the multiplication is performed in a one's complement format in a gate array assembly and then converted to a two's complement format. The gate array assembly generally multiplying successive eight bit bytes of the multiplier two bits at a time in each of four ranks to the full width multiplicand and producing a partial sum and carry at the end of each cycle. Each partial sum and carry then being fedback, aligned and added into the partial sum and carry produced during the multiplication of the next successive multiplier byte, until the multiplication is complete and at which time the final partial carry is converted and added to the final partial product to produce the final product.

REFERENCES:
patent: 3730425 (1973-05-01), Kindell et al.
patent: 3840727 (1974-10-01), Amdahl et al.
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4228520 (1980-10-01), Letteney et al.

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