Array multiplier adapted for tiled layout by silicon compiler

Details Array multiplier adapted for tiled layout by silicon compiler Array multiplier adapted for tiled layout by silicon compiler

1992-10-22

1994-03-01

Malzahn, David H.

Boots, shoes, and leggings

G06F 752

Patent

active

052914313

ABSTRACT:
An array multiplier using modified Booth encoding of multiplier input signals is formed on the surface of a monolithic integrated circuit using masks generated by a computer, in accordance with a silicon compiler program, by arranging an array of standard cells selected from a library of standard cell designs in a tessellation procedure. The array multiplier is laid out in accordance with one of particular tessellation patterns, which employ simpler and more regular patterns of interconnections between cells. Carry-save addition is used in combining partial product terms to avoid concatenating long ripple carry times.

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