Array fault testing approach for TCAMs

Details Array fault testing approach for TCAMs Array fault testing approach for TCAMs

2007-09-25

2007-09-25

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S200000

Reexamination Certificate

active

11381540

ABSTRACT:
A novel array fault testing for a TCAM system that includes a plurality of TCAM blocks that is organized into at least one rectangular array having rows each having a plurality of TCAM blocks, a group of TCAM cells and associated read/write bit lines connecting the group of TCAM cells to write driver and decoding block. The data decode bypass circuit of the TCAM cell provides a raw write feature to detect faults in a full suite of memory related tests. The debug input of the data debug bypass circuit of the TCAM cell when asserted in the test mode enables the TCAM cell to write raw, unencoded data into the array, and when deasserted in the test mode, enables the testing of the TCAM array. The resulting TCAM cell provides exhaustive fault testing thereby detecting and eliminating faults in TCAM.

REFERENCES:
patent: 6584003 (2003-06-01), Kim et al.
patent: 6965519 (2005-11-01), Park et al.
patent: 7133302 (2006-11-01), Srinivasan et al.
patent: 2005/0050408 (2005-03-01), Kaginele

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