Array device for data scrambling

Details Array device for data scrambling Array device for data scrambling

1975-04-24

1979-12-04

Birmiel, Howard A.

Telegraphy

Systems

Printing

H04K 106

Patent

active

041773551

ABSTRACT:
This specification describes an array logic chip that can be used to encipher and decipher binary data. The array logic chip contains a matrix of input and output lines with the input lines divided into groups that are each addressed by a different decoder. The digits of a block of data to be encoded are arranged in sets according to the position of the digits in the block and a different set of digits is fed into each of the decoders of the array logic chip. Substitution of new digits for the original digits in each set is accomplished in the matrix by configuration of connections between a group of input lines and output lines of the arrays and in the decoders by changing the configuration of the decoders so as to vary the input lines of the matrix selected by the input signals to the decoders. Transposition or changing of position of the digits in the block of data is accomplished in the selection of the output lines to which any given group of input lines is connected. Multiple substitutions and transpositions are accomplished by readdressing the decoders with the coded data signals on the output lines of the matrix and dynamic encoding is accomplished by continuously reconfiguring the decoders and changing the couplings between input and output lines of the matrix.

REFERENCES:
patent: 3796830 (1974-03-01), Smith
patent: 3798360 (1974-03-01), Feistel

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