Boots – shoes – and leggings
Patent
1990-02-09
1992-09-29
Eng, David Y.
Boots, shoes, and leggings
3642319, 3642328, 36493103, G06F 1580
Patent
active
051520001
ABSTRACT:
A chip array comprising a plurality of integrated circuit chips. Each chip comprises a plurality of processors, each processor including a data generation circuit for generating data and data receiving circuit for receiving data, a plurality of on-chip links for interconnecting the processors on each chip to form a processor array on the chip to facilitate the parallel transfer of data generated by the processors along selected directions in the processor array during a parallel data transfer operation, and a plurality of sets of selectively-energizable data transfer terminals. Each set of the data transfer terminals facilitates the transfer of data transmitted by processors along an edge of the processor array defined on the chip, between chips along a selected direction in the chip array during the parallel data transfer operation, with at least one set of data transfer terminals facilitating the transfer of data along at least two non-collinear directions in the chip array. A plurality of communications links connected between sets of data transfer terminals of respective chips interconnect the chips to form the chip array. The communications links that are connected to the "one set of data transfer terminals" of each chip are connected to sets of data transfer terminals of each of at least two other chips along at least two non-collinear directions in the chip array to selectively facilitate the transfer of data therethrough with at least two other chips during the parallel data transfer operation.
REFERENCES:
patent: 3364472 (1968-01-01), Sloper
patent: 4270170 (1981-05-01), Reddaway
patent: 4380046 (1983-04-01), Frosch
patent: 4523273 (1985-06-01), Adams
Eng David Y.
Jordan Richard A.
Morris Francis E.
Thinking Machines Corporation
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