Array combinatorial decoding with multiple error and erasure det

Details Array combinatorial decoding with multiple error and erasure det Array combinatorial decoding with multiple error and erasure det

1994-07-15

1997-07-01

Chung, Phung

Excavating

39518205, 371 377, 371 491, G06F 1134

Patent

active

056446950

ABSTRACT:
An apparatus and method for detecting and locating up to two symbols in error or erasures in an n.times.m A(n,m,t) parity coded bit array previously recorded on a multi-track storage device where n is a prime number, m.ltoreq.n, wherein at least one non-zero syndrome of m rotated and column summed syndromes is derived. The method includes an iterative process using an incremented tracking variable and testing of the cyclic equivalence of three derived vectors to isolate the number and location of the array column or columns containing the error or errors. Each derived vector is the modulo 2 sum of a selected syndrome and a selected rotated vector. Cyclic equivalence of between a derived vector and a selected rotated one of the other derived vectors for any given iteration establishes the error or errors and their column location or locations. An extension is shown for detecting and locating up to three errors or erasures. Correction of the errors involves parity recoding the array following parity traverses of different slopes.

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patent: 4796260 (1989-01-01), Schilling et al.
patent: 5271012 (1993-12-01), Blaum et al.
"Shift Register synthesis and BCH Decoding", IEEE Transactions on Information Theory, vol. IT-15, pp. 123-127, copyright 1969.

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