Array architecture with enhanced routing for linear asics

Details Array architecture with enhanced routing for linear asics Array architecture with enhanced routing for linear asics

1994-04-01

1995-08-08

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

257555, 257205, 257207, 257208, H01L 2970, H01L 27102

Patent

active

054401534

ABSTRACT:
A linear, bipolar-type application-specific integrated circuit includes a silicon substrate having a plurality of columns of device primitives or cells. Each cell comprises a plurality of identical NPN and PNP transistors flanking a centrally-located capacitor. Each transistor has dual emitters, bases and collectors. Open field areas are reserved on the silicon substrate on the sides of the columns of cells. Formed in these open field areas are precise thin film silicon chromium resistors. Power planes are also routed in these open field areas. A ground plane is routed in the vicinity of the centrally-located capacitor. Standard analog circuits are personalized using two layers of metallization interconnects.

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