Array architecture for long record length fast-in slow-out (FISO

Details Array architecture for long record length fast-in slow-out (FISO Array architecture for long record length fast-in slow-out (FISO

1999-04-23

2000-07-18

Tran, Andrew Q.

Static information storage and retrieval

Analog storage systems

36523003, G11C 2700

Patent

active

060916192

ABSTRACT:
A very long linear input array capable of acquiring long series of acquisition data is achieved by breaking the long linear array into a series of sub-arrays, each enabled by a "global" set of enable signals. The individual cells of the local arrays are addressed by local x-y enable signals. This arrangement permits the acquisition of very long record lengths, without sacrificing the quality of other aspects of the acquisition process to excess capacitance.

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patent: 5144525 (1992-09-01), Saxe et al.
patent: 5200983 (1993-04-01), Kogan
patent: 5406507 (1995-04-01), Knierim et al.
patent: 5526301 (1996-06-01), Saxe

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