Array address and loop alignment calculations

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

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Details

708655, 708504, 708502, G06F 752, G06F 744

Patent

active

061286397

ABSTRACT:
Division system and method support a hardware division address centrifuge to provide a flexible addressing scheme, and thus facilitates the reorganization and redistribution of data between remote and local memory blocks in a distributed memory massively parallel processing system. A flexible addressing scheme supports data organizations which can vary widely, depending on the processing task. Different data organizations in memory are supported by a PE internal address having certain bits designated as the target PE number and the remaining bits designating the offset within that PE's local memory. The PE and offset bits are distributed throughout the PE internal address to achieve various data distributions throughout memory. When a transfer occurs, the PE number bits and offset bits are separated via the centrifuge under control of a software-supplied mask. The centrifuge supports scatter-gather as well as constant-stride capabilities and is easily adaptable by the user to fit a wide variety of processing tasks.

REFERENCES:
patent: 3633018 (1972-01-01), Ling
patent: 4414642 (1983-11-01), Grube
patent: 5434995 (1995-07-01), Oberlin et al.
patent: 5586325 (1996-12-01), MacDonald et al.
patent: 5765181 (1998-06-01), Oberlin et al.

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