Arrangements having ternary-weighted parameter stepping

Details Arrangements having ternary-weighted parameter stepping Arrangements having ternary-weighted parameter stepping

2002-04-26

2003-11-04

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from multi-level codes

C370S212000

Reexamination Certificate

active

06642861

ABSTRACT:

FIELD
The present invention relates to ternary weighted arrangements. For example, it relates to arrangements (delay circuits, devices systems) including a variable delay determined on a ternary basis for use in testing set-up and hold times of a latch.
BACKGROUND
Background and example embodiments of the present invention will be described in the example context of providing variable or programmable delay between two signal paths relative to each other. However, it is stressed that both practice of embodiments of the present invention, and a scope of the appended claims, are not limited thereto.
Turning now to example background discussion, it is often necessary in electronic circuits to provide a delay of one signal in a path relative to another signal. This is especially true where it is necessary to test devices such as I/O latches within integrated circuits (ICs) so as to determine success of data capture. In this environment, it is desirable to test the exact limits on capture by sequentially changing the delay in order to determine a range (times) of successful data capture. This can be used, for example, to determine setup and hold times of a latch in input/output cells.
Various kinds of delay devices may be used for this purpose. One simple manner of doing this is to have a controlled delay block with selectable taps from various points in the block. The various taps have different values of delay. The selection of the desired delay can be accomplished, for example, by binary controls. As seen in
FIG. 1
, a latch
10
receives a data input from a driver
12
and a strobe input from a delay block
14
. The delay block receives one or more control signals from a tester or other source which selects the particular delay tap, and hence the amount of delay imposed onto the strobe signal by the delay block. By changing the delay, it is possible to test and determine the range of delays at which the latch will successfully capture the data.
Another type of delay device which may be used involves a series of delay blocks having binary step values. That is, serially-connected blocks have delay values incrementing and decrementing according to powers of 2. Thus, as shown in
FIG. 2
, the first block
21
may have four (
2
2
) units of delay, the second block
24
, two (
2
1
) units of delay, and the third block
27
, one (
2
0
) unit of delay. Each block also may include a bypass
23
,
26
,
29
so that various values of delay units may be combined. Thus, the overall
FIG. 2
arrangement has a delay block
14
that includes an input signal and an output delayed signal. One or more control signals, similar to that in
FIG. 1
, also selects the units which are bypassed. For example, the control signals may control a simple switching arrangement or multiplexer at each end of each bypass, so that the signal is either delayed by the block or bypasses it and is not delayed. Thus, the system can provide from 0 to 7 units of delay by bypassing one or more of the units. As examples, if all of units are bypassed, theoretically, 0 units of delay are provided. If none of units are bypassed, theoretically, 7 units of delay are provided.
The term “theoretically” is included in the above statements because it was recognized, for example, that even if all three bypasses were used in an attempt to match a zero strobe signal delay to a zero data signal delay, asymmetries may still exist between the parallel strobe and data signal paths, in that the switches
22
,
25
,
28
within the strobe path may introduce delay which is not within the data path.
Although both these systems are usable, they are not perfect, and it would be desirable to have a system which uses less hardware, less space on a chip and introduces fewer asymmetries, if possible.


REFERENCES:
patent: 4494228 (1985-01-01), Gutleber
patent: 4751697 (1988-06-01), Hunter et al.
patent: 6188339 (2001-02-01), Hasegawa

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