Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2011-02-01
2011-02-01
Williams, Alexander O (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257SE23024, C257SE21506, C257SE23141, C257SE23010, C257S686000, C257S685000, C257S723000, C257S696000, C257S774000, C257S773000, C257S775000, C257S776000
Reexamination Certificate
active
07880309
ABSTRACT:
An arrangement of integrated circuit dice, includes first die including a first electrical coupling site and a second die comprising a second electrical coupling site, wherein the second die is stacked onto the first die such that the first electrical coupling site is at least partially exposed, wherein the first electrical coupling site and the second electrical coupling site are directly electrically connected, and a third die arranged above the first die and the second die such that a recess is formed, wherein one of the first electrical coupling sites is arranged in the recess.
REFERENCES:
patent: 6351028 (2002-02-01), Akram
patent: 6376904 (2002-04-01), Haba et al.
patent: 6407456 (2002-06-01), Ball
patent: 6900528 (2005-05-01), Mess et al.
patent: 6972487 (2005-12-01), Kato et al.
patent: 7009852 (2006-03-01), Ying et al.
patent: 7230330 (2007-06-01), Lee et al.
patent: 7495327 (2009-02-01), Tsai et al.
patent: 7550834 (2009-06-01), Yu et al.
patent: 7582944 (2009-09-01), Fukuda et al.
patent: 7598618 (2009-10-01), Shiraishi
patent: 7800208 (2010-09-01), Otremba
patent: 2002/0195697 (2002-12-01), Mess et al.
patent: 2004/0015807 (2004-01-01), Honjou et al.
patent: 2004/0245617 (2004-12-01), Damberg et al.
patent: 2005/0116331 (2005-06-01), Tsunozaki
patent: 2005/0153480 (2005-07-01), Oka
patent: 2005/0161792 (2005-07-01), Uchida
patent: 2005/0161814 (2005-07-01), Mizukoshi et al.
patent: 2005/0170600 (2005-08-01), Fukuzo
patent: 2005/0266614 (2005-12-01), Aoyagi
patent: 2006/0091518 (2006-05-01), Grafe et al.
patent: 2006/0113650 (2006-06-01), Corisis et al.
patent: 2006/0138629 (2006-06-01), Fukazawa
patent: 2006/0166404 (2006-07-01), Corisis et al.
patent: 2006/0290005 (2006-12-01), Thomas et al.
patent: 2007/0158807 (2007-07-01), Lu et al.
patent: 2007/0210447 (2007-09-01), Kinsley
patent: 2007/0222054 (2007-09-01), Hembree
patent: 2007/0278648 (2007-12-01), Akram
patent: 2008/0054489 (2008-03-01), Farrar et al.
patent: 2008/0083977 (2008-04-01), Haba et al.
patent: 2008/0237888 (2008-10-01), Hayasaka et al.
patent: 2008/0303131 (2008-12-01), McElrea et al.
patent: 2009/0032969 (2009-02-01), Pilla
patent: 2009/0096111 (2009-04-01), Fujiwara et al.
patent: 2009/0108467 (2009-04-01), Otremba
patent: 2005-302815 (2005-10-01), None
Qimonda AG
Williams Alexander O
LandOfFree
Arrangement of stacked integrated circuit dice having a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arrangement of stacked integrated circuit dice having a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement of stacked integrated circuit dice having a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2627363