Arrangement of power supply and data input/output pads in semico

Details Arrangement of power supply and data input/output pads in semico Arrangement of power supply and data input/output pads in semico

1996-12-16

1998-11-17

Nelms, David C.

Static information storage and retrieval

Addressing

Plural blocks or banks

36523008, 365201, 365226, 365 51, G11C 800, G11C 700, G11C 502

Patent

active

058386270

ABSTRACT:
Data input/output pad portions are arranged corresponding to memory blocks and adjacent to a corresponding memory block in the center region between memory blocks, and memory blocks. Power supply pads are arranged at both ends of the center region. Power supply pad transmits a power supply voltage to data input/output pad portions, and power supply pad transmits the power supply voltage to data input/output pad portions. Power supply pad for peripheral circuitry is arranged in the center portion of the center region. A multibit test circuit is provided for each memory block. A data input/output buffer operating stably at high speed is implemented in a large storage capacity memory device which in turn accommodates a multibit test mode.

REFERENCES:
patent: 5208782 (1993-05-01), Sakuta et al.
patent: 5321646 (1994-06-01), Tomishima et al.
patent: 5390140 (1995-02-01), Tomishima et al.
patent: 5412613 (1995-05-01), Galbi et al.

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