Arrangement of memory blocks and pads

Details Arrangement of memory blocks and pads Arrangement of memory blocks and pads

1997-08-01

1999-08-24

Le, Vu A.

Static information storage and retrieval

Addressing

Plural blocks or banks

365 51, 365 63, G11C 700

Patent

active

059432853

ABSTRACT:
A semiconductor memory device adapted to enhanced functional features and a large memory capacity. The semiconductor memory device includes a semiconductor chip divided into 9 regions B1 through B9 having an identical area, in a 3.times.3 pattern. A main control block is arranged at least in a central region B9 and memory blocks are arranged respectively in the peripheral regions B1 through B8 of the 9 regions. Each of the memory blocks is controlled by the main control block and includes a data input/output circuit and a memory control circuit.

REFERENCES:
patent: 5420824 (1995-05-01), Kajimoto et al.
patent: 5604710 (1997-02-01), Tomishima et al.
Y. Nitta, et al., "A 1.6G/s Data-rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and distributed Bank Architecture", IEEE International Solid-State Circuits Conference, Feb. 10, 1996, pp. 376-377.

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