Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2005-08-16
2005-08-16
Nelms, David (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S078000, C711S002000, C711S005000, C711S104000, C711S111000, C711S115000
Reexamination Certificate
active
06930903
ABSTRACT:
Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.
REFERENCES:
patent: 4280176 (1981-07-01), Tan
patent: 4679167 (1987-07-01), Finnell
patent: 5012389 (1991-04-01), Perry
patent: 5164916 (1992-11-01), Wu et al.
patent: 5191404 (1993-03-01), Wu et al.
patent: 5226136 (1993-07-01), Nakagawa
patent: 5303123 (1994-04-01), Chandler et al.
patent: 5383148 (1995-01-01), Testa et al.
patent: 5412538 (1995-05-01), Kikinis et al.
patent: 5428762 (1995-06-01), Curran et al.
patent: 5465229 (1995-11-01), Bechtolsheim et al.
patent: 5495435 (1996-02-01), Sugahara
patent: 5513135 (1996-04-01), Dell et al.
patent: 5532954 (1996-07-01), Bechtolsheim et al.
patent: 5541448 (1996-07-01), Carpenter
patent: 5572691 (1996-11-01), Koudmani
patent: 5606717 (1997-02-01), Farmwald et al.
patent: 5631807 (1997-05-01), Griffin
patent: 5642323 (1997-06-01), Kotani et al.
patent: 5652462 (1997-07-01), Matsunaga et al.
patent: 5652861 (1997-07-01), Mayo et al.
patent: 5661339 (1997-08-01), Clayton
patent: 5691946 (1997-11-01), DeBrosse et al.
patent: 5712811 (1998-01-01), Kim
patent: 5737192 (1998-04-01), Linderman
patent: 5754408 (1998-05-01), Derouiche
patent: 5835932 (1998-11-01), Rao
patent: 5847985 (1998-12-01), Mitani et al.
patent: 5867448 (1999-02-01), Mann
patent: 5953738 (1999-09-01), Rao
patent: 5973951 (1999-10-01), Bechtolsheim et al.
patent: 5994997 (1999-11-01), Brown et al.
patent: 6021048 (2000-02-01), Smith
patent: 6072744 (2000-06-01), Kwean
patent: 6097619 (2000-08-01), Nguyen et al.
patent: 6103134 (2000-08-01), Dunn et al.
patent: 6108212 (2000-08-01), Lach et al.
patent: 6130601 (2000-10-01), Brown et al.
patent: 6151235 (2000-11-01), Kitagawa et al.
patent: 6157538 (2000-12-01), Ali et al.
patent: 6171921 (2001-01-01), Dunn et al.
patent: 6181004 (2001-01-01), Koontz et al.
patent: 6194990 (2001-02-01), Lee et al.
patent: 6215718 (2001-04-01), Koelling
patent: 6222737 (2001-04-01), Ross
patent: 6222739 (2001-04-01), Bhakta et al.
patent: 6225035 (2001-05-01), Zhang et al.
patent: 6229098 (2001-05-01), Dunn et al.
patent: 6232042 (2001-05-01), Dunn et al.
patent: 6256866 (2001-07-01), Dunn
patent: 6342164 (2002-01-01), Beuhler et al.
patent: 6349456 (2002-02-01), Dunn et al.
patent: 6353539 (2002-03-01), Horine et al.
patent: 6440318 (2002-08-01), Lee et al.
patent: 6446184 (2002-09-01), Dell et al.
patent: 6502161 (2002-12-01), Perego et al.
patent: 6532158 (2003-03-01), Buttet
patent: 6545895 (2003-04-01), Li et al.
patent: 6594167 (2003-07-01), Yamasaki et al.
patent: 6594712 (2003-07-01), Pettey et al.
patent: 6617695 (2003-09-01), Kasatani
patent: 6705877 (2004-03-01), Li et al.
patent: 6751113 (2004-06-01), Bhakta et al.
patent: 6757751 (2004-06-01), Gene
patent: 6766433 (2004-07-01), Circello et al.
patent: 2002/0088633 (2002-07-01), Kong et al.
patent: 2003/0014578 (2003-01-01), Pax
patent: 2003/0048616 (2003-03-01), Ko et al.
patent: 2003/0051091 (2003-03-01), Leung et al.
patent: 2003/0057564 (2003-03-01), Leedy
patent: 2003/0061447 (2003-03-01), Perego et al.
patent: 2003/0075789 (2003-04-01), Kawamura et al.
patent: 2003/0090879 (2003-05-01), Doblar et al.
patent: 60034054 (1985-02-01), None
PCT International Search Report dated Aug. 29, 2003 for counterpart PCT application No. PCT US/03/06978 filed Mar. 6, 2003, in 5 pages.
JEDEC Standard No. 21-C, 4.20.2-168 Pin, PC133 SDRAM Registered DIMM Design Specification, Revision 1.4, Release 11a, Feb. 2002.
JEDEC Standard No. 21-C, 4.20.3-144 Pin, PC133 SDRAM Unbuffered SO-DIMM, Reference Design Specification, Revision 1.02, Release 11.
JEDEC Standard No. 21-C, DDR SDRAM PC2100 and PC1600 DDR SDRAM Registered DIMM Design Specification, Revision 1.3, Release 11b, Jan. 2002.
JEDEC Standard No. 21-C, 4.20.5-184 Pin PC1600/2100 DDR SDRAM Unbuffered DIMM Design Specification, Revision 1.1, Release 11b.
JEDEC Standard No. 21-C, 4.20.6-200 Pin, PC2700/PC2100/PC1600 DDR SDRAM Unbuffered SO-DIMM Reference Design Specification, Revision 1.1, Release 11b, Apr. 26, 2002.
Intel, PC SDRAM Registered DIMM Design Support Document, Revision 1.2, Oct. 1998.
Intel Corporation, 66/100 MHz PC SDRAM 64-Bit Non-ECC/Parity 144 Pin Unbuffered SO-DIMM Specification, Revision 1.0, Feb. 1999.
Bhakta Jayesh R.
Pauley, Jr. Robert S.
Knobbe Martens Olson & Bear LLP
Nelms David
Netlist, Inc.
Pham Ly Duy
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