Arrangement of integrated circuits in a memory module

Details Arrangement of integrated circuits in a memory module Arrangement of integrated circuits in a memory module

2002-03-07

2004-06-15

Nelms, David (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S078000, C711S002000, C711S005000, C711S104000, C711S111000, C711S115000

Reexamination Certificate

active

06751113

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory modules for use in computers. More specifically, the invention relates to the layout and organization of SDRAM memory modules to achieve 1-Gigabyte (i.e., 1,073,741,824 bytes) or more capacity using standard TSOP integrated circuits.
2. Description of the Related Art
The demand for high speed, high capacity memory modules for use in the computer industry has grown rapidly. The average base memory capacity of servers recently increased from 512 Megabytes to 1.2 Gigabytes. The cost of dynamic random access memory (DRAM) modules declined by more than 75%.
To successfully operate in a computer, a memory module must meet standard timing and interface requirements for the type of memory module intended for use in the particular computer. These requirements are defined in design specification documents that are published by either the original initiator of the standard (e.g., Intel or IBM) or a standards issuing body such as JEDEC (formerly, the Joint Electron Device Engineering Council). Among the most important design guidelines for memory module manufactures are those for PC SDRAM, PC133 SDRAM, and DDR SDRAM. The requirements documents also provide design guidelines which, if followed, will result in a memory module that meets the necessary timing requirements.
To meet the requirements defined in the SDRAM design guidelines and respond to consumer demand for higher capacity memory modules, manufacturers of memory modules have attempted to place a higher density of memory integrated circuits on boards that meet the 1.75″ board height guideline found in the design specifications. Achieving the effective memory density on the printed circuit board has presented a substantial challenge to memory module manufacturers. High memory density on the memory module board has been achieved via the use of stacked integrated circuits and the use of more compact integrated circuit connector designs, such as micro-BGA (Ball Grid Array)
Use of non-standard integrated circuits, such as micro-BGA integrated circuits increases costs. Micro-BGA integrated circuits use a connection technique that places the connections for the integrated circuit between the body of the integrated circuit and the printed circuit board. Consequently, micro-BGA integrated circuits can be placed closer to one another on a board than can integrated circuits using the more prevalent TSOP (Thin Small Outline Package) packaging techniques. However, integrated circuits using micro-BGA connectors typically cost twice as much as comparable capacity TSOP integrated circuits.
Stacking a second layer of integrated circuits on top of the integrated circuits directly on the surface of the printed circuit board allows the manufacturer to double the memory density on the circuit board. However, the stacking of integrated circuits results in twice as much heat generation as with single layers of integrated circuits, with no corresponding increase in surface area. Consequently, memory modules using stacked integrated circuits have substantial disadvantages over memory modules using a single layer of integrated circuits. Operating at higher temperatures increases the incidence of bit failure. Greater cooling capacity is needed to avoid the problems of high temperature operation. Thermal fatigue and physical failure of the connections between the circuit board and the integrated circuit can result from ongoing heating and cooling cycles.
SUMMARY OF THE INVENTION
A first aspect of the present invention is a memory module comprising a printed circuit board and a plurality of identical integrated circuits. The integrated circuits are mounted on one or both sides of the printed circuit board in first and second rows. The integrated circuits in the first row on a side are oriented in an opposite orientation from the integrated circuits in the second row on the same side. The orientation of the integrated circuits are indicated by an orientation indicia contained on each integrated circuit.
Another aspect of the present invention is a memory module comprising a printed circuit board. A plurality of identical integrated circuits are mounted in two rows on at least one side of the printed circuit board. The memory module also includes a control logic bus, a first register and a second register. The control logic bus is connected to the integrated circuits. The first register and the second register are connected to the control logic bus. Each row of integrated circuits is divided into a first lateral half and a second lateral half. The first register addresses the integrated circuits in the first lateral half of both rows. The second register addresses the integrated circuits in the second lateral half of both rows.
Another aspect of the present invention is a memory module comprising a printed circuit board. A plurality of identical integrated circuits are mounted in two rows on at least one side of the printed circuit board. The memory module includes a control logic bus, a first register and a second register. The control logic bus is connected to the integrated circuits. The first register and the second register are connected to the control logic bus. The first register accesses a first range of data bits and a second range of data bits. The second register accesses a third range of data bits and a fourth range of data bits. The first range of data bits and the second range of data bits are non-contiguous subsets of a data word. The third range of data bits and the fourth range of data bits are also non-contiguous subsets of a data word.
A further aspect of the present invention is a method for arranging integrated circuit locations on a printed circuit board. The method comprises placing locations for the integrated circuits in a first row and a second row onto at least one surface of a printed circuit board. The integrated circuit locations in the second row are oriented 180 degrees relative to an orientation of the integrated circuit locations in the first row.
Another aspect of the present invention is a method for the manufacture of memory modules. The method comprises placing the locations for the integrated circuits on a printed circuit board in a first row and a second row on at least one side of the printed circuit board, and orienting the integrated circuit locations in the first row 180 degrees relative to the orientation of the integrated circuits in the second row. The method further comprises interconnecting the integrated circuit locations in a first half of the first row of integrated circuits and the first half of the second row of integrated circuits to a first register location, and interconnecting the integrated circuit locations in a second half of the first row of integrated circuit locations and the second half of the second row of integrated circuit locations to a second register location. The method also comprises placing identical integrated circuits at the integrated circuit locations in the printed circuit board.
Another aspect of the present invention is a 1-Gigabyte capacity memory module comprising 36 integrated circuits. The integrated circuits are 256-Megabit (i.e., 268,435,456 bits) SDRAM organized as 64 Meg by 4 bits (i.e., 67,108,864 addressed locations with 4 bits per location). The integrated circuits are in a Thin Small Outline Package (TSOP). The memory module has an approximate width of 5.25 inches (133.350 mm) and an approximate height of 2.05 inches (52.073 mm).
Another aspect of the present invention is a 2-Gigabyte capacity memory module comprises 36 integrated circuits. The integrated circuits are 512-Megabit (i.e., 536,870,912 bits) SDRAM organized as 128 Meg by 4 bits (i.e., 134,217,728 addressed locations with 4 bits per location). The integrated circuits are in a Thin Small Outline Package (TSOP). The memory module has an approximate width of 5.25 inches (133.350 mm) and an approximate height of 2.05 inches (52.073 mm).


REFERENCES:
patent: 5012389 (1991-04-01), Perry
patent: 5164916 (1992-11-01

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