Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2006-07-14
2010-06-29
Ghyka, Alexander G (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C438S598000, C438S599000, C257SE21575
Reexamination Certificate
active
07745239
ABSTRACT:
An integrated circuit having a metal interconnect layer, and also having a conductive line and a boundary defined with a uniform distance from the conductive line that defines a “keep out” distance between the boundary and the conductive line. A set of first fill elements are uniformly arranged along the boundary outside of the “keep out” distance, and a set of second fill elements further from the conductive line than the first fill elements are arranged in a pattern that would be uniform, but for having some fill elements missing from the pattern.
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Gupta Puneet
Kahng Andrew B.
Nakagawa O. Samuel
Wong Pakman
Ghyka Alexander G
Martine & Penilla & Gencarella LLP
Nikmanesh Seahvosh J
Tela Innovations, Inc.
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