Patent
1985-02-07
1986-04-22
Edlow, Martin H.
357 68, 357 45, H01L 2702, H01L 2710, H01L 2950
Patent
active
045845956
ABSTRACT:
A circuit arrangement for FETs connected in parallel. In the arrangement the same electrode of N FETs (N>1) is connected by associated metallic conductors to a central conductor. A further metallic conductor is also connected to the central conductor. The shape of the central conductor is such that the FETs are mechanically equidistant from the connection of the further conductor. This equalizes the fall times between the FETs without the need to add any physical inductors to the circuit.
REFERENCES:
patent: 4529999 (1985-04-01), Bender
Edlow Martin H.
Henn Terri M.
Reliance Electric Company
Rickin Michael M.
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