Arrangement of controlling issue timing of a read instruction to

Details Arrangement of controlling issue timing of a read instruction to Arrangement of controlling issue timing of a read instruction to

1995-05-08

1996-07-30

Lall, Parshotam S.

Boots, shoes, and leggings

395550, 395800, 364DIG1, G06F 934

Patent

active

055420613

ABSTRACT:
In order to effectively accelerate issue of a RAM read instruction which is to access the same memory block as a preceding RAM write instruction, when the RAM write instruction is issued, a counter initiates counting-up of a value indicative a predetermined time duration. When the counter counts up the value, the RAM read instruction is allowed to be issued at appropriate timing. A time duration for which the RAM read instruction is prohibited to be issued, is much shorter than a time duration which expires when the RAM write instruction is completely finished. Thus, the RAM read instruction issue is not required to wait for the completion of execution of the RAM write instruction as in a known technique.

REFERENCES:
patent: 4594682 (1986-06-01), Drimak
patent: 4739472 (1988-04-01), Hayashi
patent: 4789925 (1988-12-01), Lahti
patent: 5001626 (1991-03-01), Kashiyama et al.
patent: 5014196 (1991-05-01), Hayashi et al.
patent: 5125083 (1992-06-01), Fite et al.
patent: 5297139 (1994-03-01), Okura et al.

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