Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
2007-11-26
2011-12-20
Mai, Tan V (Department: 2193)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
08082283
ABSTRACT:
A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells. Each LUT logic cell is configured to receive three operand signals at three inputs of that LUT logic cell and to output two signals at two outputs of that LUT logic cell that are a sum and carry signal resulting from adding the operand signals. LAB internal routing logic couples the LUT logic cells such that the LUT logic cells collectively process the input signals to generate the output signals. The LAB internal routing logic is not part of the PLD routing architecture. By employing compressor LUT logic cells within the LAB, use of PLD routing architecture is minimized, and use of PLD resources is more efficient.
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Altera Corporation
Mai Tan V
Weaver Austin Villeneuve & Sampson LLP
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