Arrangement of 3-input LUT's to implement 4:2 compressors...

Details Arrangement of 3-input LUT's to implement 4:2 compressors... Arrangement of 3-input LUT's to implement 4:2 compressors...

2007-11-27

2007-11-27

Do, Chat C. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10660903

ABSTRACT:
A programmable logic device (PLD) includes a plurality of logic array blocks (LAB's) connected by a PLD routing architecture. At least one LAB is configured to determine a compression of a plurality of N-bit numbers. The LAB includes look-up table (LUT) logic cells. Each look-up table (LUT) logic cell is configured to input three operand signals at three respective inputs of that look-up table (LUT) logic cell and to output two signals at two respective outputs of that look-up table logic cell (LUT) that are a sum and carry signal resulting from adding the three input signals. By employing 3:2 compressor LUT logic cells within the LAB for addition, the use of the routing resources in the PLD is minimized.

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Heriot-Watts, User Configurable Logic, Sep. 1992, IEEE computing & Control Engineering Journal, pp. 205-213.

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