Arrangement in a self-guarding data processing system for system

Details Arrangement in a self-guarding data processing system for system Arrangement in a self-guarding data processing system for system

1989-08-31

1992-10-13

Anderson, Lawrence E.

Boots, shoes, and leggings

395550, 395575, 364DIG1, 364259, 3642599, 3642802, 364270, 3642445, G06F 1300

Patent

active

051558564

ABSTRACT:
In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation, e.g., processing/logging error data, prior to a processor start. One or more reset areas are defined which are initialized/reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause, e.g., power-on, for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.

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"A Logic Design Structure for LSI Testability" by E. B. Eichelberger, Proceedings of the Design Automation Conference, No. 14, 20-22, Jun. 1977, New Orleans, La., pp. 462-468.

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