Patent
1995-05-22
1997-03-04
Auve, Glenn A.
395282, 395886, G06F 1300
Patent
active
056088825
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention concerns an arrangement for transmitting data over a bus having a central unit which initiates data transmission and one or several peripheral units linked to each other by the bus.
An arrangement of this sort is known from the DE-PS 31 33 407. There, a processor as a central unit is connected to a memory as a peripheral unit by a bus. The bus contains data lines whose number corresponds to the word width, address lines for addressing the individual memory cells and control lines for controlling the data transmission. Data transmission can take place selectably as 8-bit-wide byte accesses or 16-bit-wide word accesses. To select the access mode, besides READ and WRITE signals, a BYTE signal is also provided which is evaluated in a control signal decoder. The processor executes a fixed microprogram which is tailored to the special hardware configuration. A change in the number of data lines thus leads necessarily to a change in the microprogram. For example, the memory cannot be easily replaced by a memory of another data width.
In electronic, modularly designed devices in which the components central unit, peripheral unit and bus are interchangeable, there exist both cost-effective devices with a small data bus width as well as devices of the upper class of capacity which are characterized by a data bus of large width.
The underlying object of the invention is to create an arrangement in which the components of different classes of capacity can be combined together in any way.
SUMMARY OF THE INVENTION
The present invention achieves this objective by providing an arrangement for transmitting data over a bus having a central until which initiates data transmission and one or more peripheral units linked to each other by the bus, the units and the bus having first control lines for a first transmission request signal of the central unit and for a first transmission acknowledgement signal of a peripheral unit for parallel transmission of a data word of a first data width and at least one unit and/or the bus having second control lines for parallel transmission of a data word of a second data width, which carry a second transmission request signal and a second transmission acknowledgement signal, such that the second transmission request signal in the peripheral unit and the second transmission acknowledgement signal in the central unit assume an active state only if all devices involved in the transmission have second control lines.
In the arrangement the second data width can be a multiple of the first. In fact, there can be three different data widths achievable, 8 bits, 16 bits and 32 bits. The units can be plug-in modules while the bus can constitute a rear panel wiring of a card rack. The arrangement can include a further control line to indicate bus usage which is activated during transmission of the data word of the second data width if not all devices involved in the transmission have second control lines such that the data word of a second data width is transmitted through transmission of a number corresponding to the multiple of successive data words of the first data width.
The invention has the advantage that components of different classes of capacity can be combined together in a modular device. To connect a central unit or peripheral units to the bus, which can be designed as rear-panel wiring in a card rack, no particular card slots suitable only for modules of specific classes of capacity are required. The modules of different classes of capacity can be arranged according to the invention in any given slot. For example, the operation of modules having a 32-bit data bus width is possible in a card rack having an 8-bit data bus width in the rear-panel wiring. The invention allows in this manner a gradual increase in capacity from 8-bit to 32-bit data bus width by exchanging individual components as part of a quasi-flowing transition without having to exchange the entire device in one step. The arrangement according to the invention allows the
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Electronic Design, vol. 33, No. 12, Jan. 24, Hasbrouck Heights, NJ, pp. 219-225, C. K. Zoch et al.: 68020 Dynamically Adjusts its Data Transfers to Match Peripheral Ports.
Abert Michael
Block Siegfried
Bozenhardt Johannes
Leigsnering Franz
Pfatteicher Werner
Auve Glenn A.
Siemens Aktiengesellschaft
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