Arrangement for the display of processing data by means of pixel

Details Arrangement for the display of processing data by means of pixel Arrangement for the display of processing data by means of pixel

1988-02-29

1989-10-17

Brigance, Gerald

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340811, 340814, 358140, G09G 116

Patent

active

048750352

ABSTRACT:
The logic signals (S0, S1, S2, HL) which define the pixel are combined together with the synchronization signals (HS, VS) by a composer circuit (19) disposed in the display control, to form a single composite signal. The composer circuit (19) is connected by way of a single conductor (21) to a separator circuit (29) for separating the synchronizing signal, disposed in the VDU control circuit (20). The VDU control circuit comprises horizontal and vertical deflection circuits (27, 43 and 28, 44) for a CRT (24) and further comprises a format selector circuit (30) which is capable of sensing the duration of the vertical synchronizing pulse to control the frequency of the video signal vertical deflection circuit (28, 44).

REFERENCES:
patent: 3651253 (1972-03-01), Morgand et al.
patent: 4296476 (1981-10-01), Mayer et al.
patent: 4338597 (1982-07-01), Steiner et al.
patent: 4574279 (1986-03-01), Roberts
patent: 4725833 (1988-02-01), Nakamura

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