Arrangement for synchronizing a byte clock derived from a data b

Details Arrangement for synchronizing a byte clock derived from a data b Arrangement for synchronizing a byte clock derived from a data b

1987-09-08

1988-12-20

Pellinen, A. D.

Pulse or digital communications

Spread spectrum

Direct sequence

375117, 370102, H04L 700, H04J 306

Patent

active

047929669

ABSTRACT:
In a terminal equipment connected to a packet-oriented, ring-shaped network, a comparator identifies the beginning and the presence of a start of packet information after a series-to-parallel conversion of the data bit stream, whereby filler information are transmitted between the packets. With the recognition of the beginning of the start of packet information, a counter arranged in a byte clock generator is arrested and is reset given the presence of the complete start of packet information so that an internal, current byte clock pulse is lengthened and, therefore, the packet byte clock is synchronized with the byte clock inherent in the terminal equipment.

REFERENCES:
patent: 3983325 (1976-09-01), Ollinger et al.
patent: 4101732 (1978-07-01), Suzuki
patent: 4674088 (1987-06-01), Grover
"FDDI Physical Layer Protocol (PHY)" Proposed Draft for Standards, Computer & Business Equipment Manufactures Association, Aug. 22, 1986.

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