Arrangement for switching a clock to a clock having the same fre

Details Arrangement for switching a clock to a clock having the same fre Arrangement for switching a clock to a clock having the same fre

1989-11-27

1992-03-24

Olms, Douglas W.

Pulse or digital communications

Spread spectrum

Direct sequence

375118, 328 63, 328 55, H03D 324

Patent

active

050995014

ABSTRACT:
A circuit arrangement has a control logic stage, a clock monitoring stage, and a clock selector stage. The control logic stage includes a shift register having register cells that are identical with the exception of the first. The identical shift registers have a D-flip-flop in which a pre-control signal is formed by intermediate storage of a control signal. A pre-control signal arises in the first register cell when all other pre-control signals are absent. The switching ensues dependent on a correction signal and the clocks at the affected registered cells such that the previous control signal is first disconnected before the new control signal is engaged. In the clock selector stage, the active control signal through-connects the allocated clock as auxiliary data clock. The clock monitoring stage generates a start signal when either no control signal is present or when a plurality of control signals were erroneously formed at the same time. Such a circuit arrangement is employable in the clock recovery in digital signal multiplex devices.

REFERENCES:
patent: 4604582 (1986-08-01), Strenkowski et al.
patent: 4841548 (1989-06-01), Volejnik
patent: 4841551 (1989-06-01), Ajaneas
patent: 4942590 (1990-07-01), Terada
patent: 4975929 (1990-12-01), Apple et al.

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