Arrangement for simultaneously translating logical page addresse

Details Arrangement for simultaneously translating logical page addresse Arrangement for simultaneously translating logical page addresse

1990-12-19

1994-04-12

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG2, 364955, 3649555, G06F 1210

Patent

active

053033590

ABSTRACT:
A predetermined number of logical page addresses are effectively translated into corresponding real ones. The number of the logical page addresses is determined by (M+N) bits and, each of the logical page addresses includes upper M-bit and lower N-bit. Logical page address registers, whose number is equal to 2.sup.N, are provided to respectively store the predetermined number of logical page addresses applied. Address translation buffers (whose number is also equal to 2.sup.N) each stores 2.sup.M real page addresses which are grouped according to each of the lower N bits. The address translation buffers receive the upper M-bit of one of the logical page addresses, and output real addresses. An address translation controller receives the outputs of the address translation buffers and also receives the lower N-bit, and selects the real page addresses using the lower N-bit. The selected real page addresses are applied to a plurality of real address registers. A page number comparator determines whether or not the upper M-bit of one of the logical page address coincides with the upper M-bit of each of the remaining logical page addresses. The page number comparator outputs the comparison results which allow the real address(es) stored in the real address registers to be applied to a main memory.

REFERENCES:
patent: 3825904 (1974-07-01), Burk et al.
patent: 4332010 (1982-05-01), Messina et al.
patent: 4491911 (1985-01-01), Sato
patent: 4691281 (1987-09-01), Furui

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