Arrangement for simultaneously dealing with transfer requests pr

Details Arrangement for simultaneously dealing with transfer requests pr Arrangement for simultaneously dealing with transfer requests pr

1988-12-27

1992-04-21

Olms, Douglas W.

G06F 100

Patent

active

051074168

ABSTRACT:
For transfer of memory contents between an extended buffer memory and one of a first and a second main memory and of a peripheral storage device connected to an input-output processor, a transfer controlling arrangement can simultaneously receive transfer requests produced by a central processor, an arithmetic processor, and the input-output processor and can control the transfer requests. The transfer controlling arrangement comprises an extended buffer memory transfer controller connected to the central and the input-output processors through a first transfer controller, to the arithmetic processor through a second transfer controller, and to the extended buffer memory.

REFERENCES:
patent: 3510844 (1966-07-01), Aranyi et al.
patent: 3510845 (1966-09-01), Couleur et al.
patent: 3514758 (1967-03-01), Bennett
patent: 3525080 (1968-02-01), Couleur et al.
patent: 4100601 (1978-07-01), Kaufman
patent: 4484263 (1984-11-01), Olson et al.

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