Arrangement for selective generation of an output signal related

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Frequency or repetition rate conversion or control

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327117, 327 99, 327299, 377 47, H03K 21117

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active

058282491

ABSTRACT:
A dynamic latching arrangement with a conditional driver, a system, and a method reduce power consumption, increase operating speed, and reduce the number of discrete components. The conditional driver selectively impresses a signal on an internal node of the circuit such that when a control signal is asserted, a signal related to the clock signal is generated, but when the control signal is not asserted, a different signal related to the clock signal is generated.

REFERENCES:
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patent: 4464586 (1984-08-01), Henning
patent: 5148050 (1992-09-01), Koide
M. Afghahi, A Robust Single Phase Clocking for Low Power, High-Speed VLSI Applications, IEEE Journal of Solid-State Circuits, vol. 31, No. 2, Feb., 1996, pp. 247-254.
Richard X. Gu et al., All-N-Logic High-Speed True-Single-Phase Dynamic CMOS Logic, IEEE Journal of Solid-State Circuits, vol. 31, No. 2, Feb., 1996, pp. 221-229.
Jiren Yuan et al., High-Speed CMOS Circuit Technique, IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb., 1989, pp. 62-69.

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