Arrangement for reducing stress in substrate-based chip...

Details Arrangement for reducing stress in substrate-based chip... Arrangement for reducing stress in substrate-based chip...

2007-02-20

2007-02-20

Thai, Luan (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

C257S784000, C257S780000, C257SE23063

Reexamination Certificate

active

10850832

ABSTRACT:
An arrangement reduces stress in substrate-based chip packages, in particular of Ball Grid Arrays (BGA) with rear-side and/or edge protection. The chip is firmly connected to a substrate, which is provided on the side that is opposite from the chip with conducting tracks and micro-balls for making electrical contact with the next-higher wiring level. Regular trench-shaped structures are introduced into the substrate on the chip side thereof and at least enclosing the chip, in order to interrupt or shift the thermally induced mechanical stress in the substrate, indicated by the chip.

REFERENCES:
patent: 5218234 (1993-06-01), Thompson et al.
patent: 5293067 (1994-03-01), Thompson et al.
patent: 5391916 (1995-02-01), Kohno et al.
patent: 5914531 (1999-06-01), Tsunoda et al.
patent: 5953589 (1999-09-01), Shim et al.
patent: 6291264 (2001-09-01), Tang et al.
patent: 7005737 (2006-02-01), Zhao et al.
patent: 101 27010 (2002-12-01), None

Affiliated with

Also associated with

Rating

Arrangement for reducing stress in substrate-based chip... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Arrangement for reducing stress in substrate-based chip..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement for reducing stress in substrate-based chip... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3887222