Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-02-11
2004-04-27
Pham, Chi (Department: 2667)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S469000, C709S242000
Reexamination Certificate
active
06728246
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to layer
2
and layer
3
switching of data packets in a non-blocking network switch configured for switching data packets between subnetworks.
2. Background Art
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interface devices at each network node to access the network medium.
The Ethernet protocol IEEE 802.3 has evolved to specify a half-duplex media access mechanism and a full-duplex media access mechanism for transmission of data packets. The full-duplex media access mechanism provides a two-way, point-to-point communication link between two network elements, for example between a network node and a switched hub.
Switched local area networks are encountering increasing demands for higher speed connectivity, more flexible switching performance, and the ability to accommodate more complex network architectures. For example, commonly-assigned U.S. Pat. No. 5,953,335 discloses a network switch configured for switching layer
2
type Ethernet (IEEE 802.3) data packets between different network nodes; a received data packet may include a VLAN (virtual LAN) tagged frame according to IEEE 802.1q protocol that specifies another subnetwork (via a router) or a prescribed group of stations. Since the switching occurs at the layer
2
level, a router is typically necessary to transfer the data packet between subnetworks.
Efforts to enhance the switching performance of a network switch to include layer
3
(e.g., Internet protocol) processing may suffer serious drawbacks, as current layer
2
switches preferably are configured for operating in a non-blocking mode, where data packets can be output from the switch at the same rate that the data packets are received. Newer designs are needed to ensure that higher speed switches can provide both layer
2
switching and layer
3
switching capabilities for faster speed networks such as 100 Mbps or gigabit networks.
However, such design requirements risk loss of the non-blocking features of the network switch, as it becomes increasingly difficult for the switching fabric of a network switch to be able to perform layer
3
processing at the wire rates (i.e., the network data rate). For example, switching fabrics in layer
2
switches merely need to determine an output port for an incoming layer
2
data packet. Layer
3
processing, however, requires implementation of user-defined policies that specify what type of data traffic may be given priority accesses at prescribed intervals; for example, one user defined policy may limit Internet browsing by employees during work hours, and another user-defined policy may assign a high priority to e-mail messages from corporate executives.
One difficulty encountered and layer
3
processing is the substantial overhead that layer
3
switching logic must perform before actually performing the layer
3
switching decisions. For example, one layer
2
switch has a switching module that is configured to monitor layer
2
, and possibly layer
3
, header information as the layer
2
data packet is being transferred from a network switch port to a buffer memory; hence, the switching module is able to “snoop” on the first forty bytes of a received data packet for layer
2
and layer
3
header information during transfer from a network switch port to buffer memory. However, the switching module then needs to parse the layer
2
header and the layer
3
header to obtain the relevant address information for performing layer
2
or layer
3
switching decisions. This parsing of the layer
2
header and layer
3
header by the switching module imposes substantial processing burdens on the switching module that affects the cost of the network switch, and may adversely affect the ability of the network switch to perform layer
3
processing at the wire rate.
SUMMARY OF THE INVENTION
There is a need for an arrangement that enables a network switch to provide layer
2
switching and layer
3
switching capabilities for 100 Mbps and gigabit links without blocking of the data packets.
There is also a need for an arrangement that enables a network switch to provide layer
2
switching and layer
3
switching capabilities with minimal buffering within the network switch that may otherwise affect latency of switched data packets.
There is also a need for an arrangement that enables a switching module of a network switch to perform layer
3
processing of user-defined policies at the network wire rate on layer
2
data packets, without the necessity of parsing incoming layer
2
and layer
3
headers for switching information.
These and other needs are attained by the present invention, where a network switch includes network switch ports, each including a port filter configured for obtaining and filtering relevant layer
3
information from a received layer
2
frame. Each port filter, upon filtering the relevant layer
3
information from a received layer
2
frame, outputs the relevant layer
3
information to switching logic, enabling the switching logic to perform layer
3
processing to determine a layer
3
switching operation to be performed on the received layer
2
frame. Hence, the switching logic performs the layer
3
processing based on the relevant layer
3
information, without the necessity of parsing the received layer
3
information by the switching logic.
One aspect of the present invention provides a method in a network switch. The method includes receiving a first layer
2
frame at a network switch port, the first layer
2
frame including layer
3
header information. The method also includes outputting selected portions of the layer
3
header information from the network switch port, and generating a layer
3
switching decision in a switching module based on the selected portions of the layer
3
header information. The outputting of selected portions of the layer
3
header information from the network switch port ensures that the switching module receives only relevant layer
3
header information, enabling the switching module to generate the layer
3
switching decision based on the selected portions of the layer
3
header information, without the necessity of any parsing by the switching module. Moreover, the outputting of the selected portions of the layer
3
header information by the network switch port enables each of the network switch ports to provide distributed processing of incoming layer
3
data, eliminating the necessity of processing overhead by the switching module. Hence, the switching module can be optimized for performing layer
3
switching decisions, as opposed to performing overhead functions such as parsing layer
3
header information to eliminate nonrelevant data.
Another aspect of the present invention provides an integrated network switch configured for executing layer
3
switching decisions, the integrated network switch having network switch ports. Each network switch port comprises a port filter configured for obtaining layer
3
information from a received layer
2
frame and outputting portions of the layer
3
information based on a determined relevance of the portions for generation of a layer
3
switching decision. The network switch also includes a switching module for generating the layer
3
switching decision based on the portions of the layer
3
information. Hence, each network switch port can easily filter nonrelevant layer
3
information, and output only those portions of the layer
3
information, to the switching module, which are relevant to generation of a layer
3
switching decision. Hence, layer
3
processing overhead within the switching module is minimized.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages
Egbert Chandan
Kanuri Mrudula
Advanced Micro Devices , Inc.
Manelli Denison & Selter PLLC
Pham Chi
Qureshi Afsar M.
Turkevich Leon R.
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