Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-05-09
2004-10-19
Pezzlo, John (Department: 2662)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S409000
Reexamination Certificate
active
06807183
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to buffering of data packets in a non-blocking network switch configured for switching data packets.
2. Background Art
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interface devices at each network node to access the network medium.
The Ethernet protocol IEEE 802.3 has evolved to specify a half-duplex media access mechanism and a full-duplex media access mechanism for transmission of data packets. The full-duplex media access mechanism provides a two-way, point-to-point communication link between two network elements, for example between a network node and a switched hub.
Switched local area networks are encountering increasing demands for higher speed connectivity, more flexible switching performance, and the ability to accommodate more complex network architectures. For example, commonly-assigned U.S. Pat. No. 5,953,335 discloses a network switch configured for switching layer
2
type Ethernet (IEEE 802.3) data packets between different network nodes; a received data packet may include a VLAN (virtual LAN) tagged frame according to IEEE 802.1q protocol that specifies another subnetwork (via a router) or a prescribed group of stations. Since the switching occurs at the layer
2
level, a router is typically necessary to transfer the data packet between subnetworks.
Efforts to enhance the switching performance of a network switch to include layer
3
(e.g., Internet protocol) processing may suffer serious drawbacks, as current layer
2
switches preferably are configured for operating in a non-blocking mode, where data packets can be output from the switch at the same rate that the data packets are received. Newer designs are needed to ensure that higher speed switches can provide both layer
2
switching and layer
3
switching capabilities for faster speed networks such as 100 Mbps or gigabit networks.
However, such design requirements risk loss of the non-blocking features of the network switch, as it becomes increasingly difficult for the switching fabric of a network switch to be able to perform layer
3
processing at the wire rates (i.e., the network data rate).
Commonly-assigned, copending application Ser. No. 09/430,753, filed Oct. 29, 1999, entitled Apparatus and Method for Identifying Data Packet Types in Real Time on a Network Switch Port discloses a network switch having a plurality of network switch ports, each network switch port having a filter (i.e., a packet classifier module) configured for evaluating an incoming data packet on an instantaneous basis. The filter performs simultaneous comparisons between the incoming data stream of the data packet and multiple templates configured for identifying respective data protocols.
A particular concern in implementing the above-described packet classifier module in each network switch port is minimizing the latency encountered between reception of the incoming data stream and actual comparison of the received data stream with the multiple templates. Although network switch ports conventionally have a first and first-out (FIFO) buffer for storing frame data received by the MAC, such FIFO buffers are not configured for enabling a packet classifier module to evaluate selected portions of the incoming frame data.
SUMMARY OF THE INVENTION
There is a need for an arrangement that enables a network switch to provide evaluation of an incoming data stream for 100 Mbps and gigabit links without blocking of the data packets and with minimal latency and complexity.
There is also a need for an arrangement that enables a packet classifier module within a network switch port to quickly access selected portions of an incoming data stream during reception by the network switch port.
These and other needs are attained by the present invention, where a network switch port having a packet classifier includes buffer read logic that enables the packet classifier to read selected portions of the incoming frame data as the incoming frame data is received by the network switch port.
One aspect of the present invention provides a method in a network switch port. The method includes the steps of determining whether a first in first-out (FIFO) buffer, configured for storing frame data of a received data packet, has stored a selected byte of the received data packet, and selectively generating a signal indicating availability of reading the selected byte of the received data packet within the FIFO buffer, based on the determination that the FIFO buffer has stored the selected byte. The selective generation of the signal indicating availability of reading the selected byte enables the network switch port to read the selected byte within the FIFO buffer, independent of the remaining frame data in the FIFO buffer. Hence, the network switch port can perform evaluations of selected bytes of the received data packet as the selected bytes are received, independent of the buffering of the entire received data frame.
Another aspect of the present invention provides an integrated network switch having a plurality of network switch ports. Each network switch port includes a media access control FIFO configured for storing frame data of a received layer
2
type data packet, the received layer
2
type data packet having a layer
2
header and a layer
2
payload, and a packet classifier module. The packet classifier module is configured for evaluating selected data bytes of the layer
2
payload, the packet classifier module including buffer read logic configured for reading the selected data bytes based on determined reception by the network switch port. Hence, the buffer read logic enables the packet classifier module to read the selected data bytes of the layer
2
payload, without extracting the entire received data packet from the media access control FIFO.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.
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Gupta, P. et al. “Classifying Packets with Hierarchical Intelligent Cuttings”. IEEE Micro. Stanford Univ., Ca. Jan./Feb. 2000. vol. 20, iss 1. pp 34-41.*
Borg, N. et al. “Efficient Multi-Field Packet Classification for QoS Purposes”. IWQoS '99. Seven International Workshop on Quality of Service, 1999. London, UK. May-Jun. 1999. pp. 109-118.
Chow Peter Ka-Fai
Tzeng Shr-jie
Advanced Micro Devices , Inc.
Manelli Denison & Selter PLLC
Mills Donald
Pezzlo John
Turkevich Leon R.
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