Arrangement for providing data signals for a data display system

Details Arrangement for providing data signals for a data display system Arrangement for providing data signals for a data display system

1983-10-18

1986-11-25

Brigance, Gerald L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

G09G 114

Patent

active

046252037

ABSTRACT:
The present invention includes a microprocessor which acts to generate groups of its signals from its read only memory (ROM) thereby forming character representations of groups of coded signals, such as ASCII coded signals, coming from a main data processing device. The groups of bit signals are temporarily stored in a buffer which at a subsequent time transmits, in parallel, groups of said bit signals to a bit map memory through some logic circuitry. The group, or block, transfer of said bit signals in parallel, occurs during horizontal or vertical blank periods. The parallel transfer during the blank periods provides part of the basis for acceleration of the data to a display device as compared with the prior art. In addition, the microprocessor provides address information signals to a graphic display controller, which in turn provides starting addresses, for the locations of the bit signals. In addition a bit map memory device is employed to provide pixel information to a CRT display device to create the characters which are to be shown.

REFERENCES:
patent: 4240075 (1980-12-01), Bringol
patent: 4399435 (1983-08-01), Urabe
patent: 4486746 (1984-12-01), Walker
patent: 4496944 (1985-01-01), Collmeyer et al.

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