Arrangement for program interruption

Details Arrangement for program interruption Arrangement for program interruption

1978-11-20

1981-01-27

Nusbaum, Mark E.

Boots, shoes, and leggings

G06F 946

Patent

active

042478944

ABSTRACT:
In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests--e.g., supervisor programs--a pre-settable interval timer is provided for operating after a predetermined time interval to force the setting of a PIRR bit and thereby force control to be transferred eventually to such programs.

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Forgie, "The Lincoln TX-2 I/O System", pp. 156-160, 1957.
Dennison et al., "Internal Masking of Interrupts", IBM TDB vol. 20, No. 8 pp. 3277-3278.

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