Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-06-12
2001-10-09
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S156000
Reexamination Certificate
active
06300808
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to an arrangement for offset current compensation of a phase detector which is provided in a phase-locked loop to which an acquisition circuit is assigned which, in a switch-on phase of the phase-locked loop, supplies acquisition pulses to a loop filter arranged in the phase-locked loop before applying an input signal to the phase-locked loop so as to bring the operating frequency of a controllable oscillator in the phase-locked loop within a predetermined frequency window.
A phase-locked loop to which an acquisition circuit is assigned is known from PCT application 98-5355482 (PHN 16366). The acquisition circuit is used to bring the operating frequency of the controllable oscillator of this phase-locked loop within a frequency window after the current supply has been switched on and/or after a reset of the phase-locked loop, so as to enable the phase-locked loop to lock in on its frequency when an input signal is applied to the phase-locked loop. Particularly in the case of a narrow band construction of the phase-locked loop, this is necessary because the phase-locked loop will otherwise be unable to lock in the frequency of the input signal. This acquisition circuit thus supplies the kind of lock-in. This is realized by acquisition pulses which are fed to the loop filter and control the frequency of the controllable oscillator until its frequency is within the frequency window.
This arrangement is suitable as a lock-in in that it simplifies lock-in of the phase-locked loop on an input signal, but it is not capable of compensating offset currents of the phase detector. When the phase detector of the phase-locked loop is beset with offset currents, lock-in of the phase-locked loop on the frequency of the input signal can as yet be ensured by the acquisition circuit, but the phase-locked loop does not operate properly because it must constantly compensate the offset current of its phase detector. This in turn means that the two input signals of the phase detector are not in the desired phase position with respect to each other but in a deviating phase position which is caused by the fact that the offset current of the phase detector must be quasi compensated.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an arrangement for compensating the offset current of the phase detector in such a phase-locked loop, to which an acquisition circuit is assigned.
According to the invention, this object is solved in that the arrangement (
1
) determines an offset correction current during at least one time interval of the switch-on phase when acquisition pulses occur, which offset correction current serves for compensating the offset current of the phase detector, the value and the sign of the offset correction current being selected in dependence upon the rate and sign of the acquisition pulses in such a way that no acquisition pulses occur any longer or occur very rarely at the end of the switch-on phase, and in that the arrangement superimposes the offset correction current thus determined on the output signal of the phase comparator also during operation of the phase-locked loop outside the switch-on phase.
The arrangement for offset current compensation according to the invention utilizes the acquisition circuit and the acquisition pulses supplied by this circuit for compensating the offset current of the phase comparator. In fact, when acquisition pulses also occur when the operating frequency of the controllable oscillator is at least temporarily within the predetermined frequency window, then this indicates that the operating frequency of the controllable oscillator is influenced by an offset current. Consequently, the arrangement supplies an offset correction current during at least a time interval of the switch-on phase, particularly an interval towards the end of the switch-on phase, when acquisition pulses occur. This offset correction current serves for compensating the offset current of the phase detector of the phase-locked loop and can be fed either directly to the phase-locked loop or to the phase detector itself. Dependent on how many acquisition pulses occur and which signs they have, the offset correction current is determined in such a way that possibly no acquisition pulses occur any longer at the end of the switch-on phase. This means that the operating frequency of the controllable oscillator is stable, which is a result of the offset current compensation because then the phase detector no longer supplies any offset current which would result in a drift of the operating frequency of the controllable oscillator.
The offset correction current is determined at least during a time interval of the switch-on phase. In the simplest case, the determination of the value of the offset correction current and its sign may be effected during the entire switch-on phase. At the start of the switch-on phase, a false offset correction current would then be determined, because in this phase the frequency of the controllable oscillator was not yet brought within the frequency window anyway by the acquisition circuit. Towards the end of the switch-on phase, whose length is chosen to be such that the acquisition circuit is capable in any case of bringing the frequency of the controllable oscillator within the frequency window, the frequency window should, however, be reached and the determination of the offset correction current would lead to the correct determination of the offset correction current in this final phase of the switch-on phase. It is also possible and even advantageous to determine the offset correction current during a time interval of the switch-on phase which lies at the end of the switch-on phase, because it is then most likely that the occurrence of the acquisition pulses is exclusively caused by offset correction currents.
The above-described mode of operation of the arrangement and the determination of the offset correction currents takes place during the switch-on phase in which no input signal is applied to the phase-locked loop. When the offset correction current has been determined by the arrangement according to the invention and when the switch-on phase has been terminated, the input signal on which the phase-locked loop should lock in is applied to the phase-locked loop. It is essential that the determined offset correction current also remains switched on after the end of the switch-on phase because it should now serve for correction of the offset current of the phase detector of the phase-locked loop in its normal mode of operation, where it unfolds its proper activity. In contrast to the acquisition pulses, which are no longer switched during normal operation of the phase-locked loop, the offset correction current remains switched on.
This results in an optimal mode of operation of the phase-locked loop because it no longer operates asymmetrically, even when the phase detector supplies an offset current, because the offset current is compensated by the offset correction current of the arrangement according to the invention. Independent of the existence and the value of an offset current, an optimal mode of operation of the phase-locked loop is thus always guaranteed. This is particularly important because such phase-locked loops are generally integrated and the tolerances of the circuit elements in such an integrated circuit are relatively large so that, due to asymmetries and other effects, an integrated phase detector often supplies offset currents which are not infrequently also so large that the entire circuit becomes unusable. Due to the arrangement according to the invention, such circuits, which would be unusable, can optimally operate because of the offset current compensation and do not have to be considered as rejects.
In an embodiment of the invention as defined in claim
2
, the value and sign of the offset correction current is determined in steps. The arrangement operates in so-called correction cycli, with the occurrence of an acquisition pulse and possibly its sign bein
Biren Steven R.
Nguyen Linh
U.S. Philips Corporation
Wells Kenneth B.
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