Arrangement for low power clock generation

Details Arrangement for low power clock generation Arrangement for low power clock generation

2005-09-13

2005-09-13

Mis, David (Department: 2817)

Oscillators

Amplitude control or stabilization

Automatic

C331S074000, C331S1160FE, C331S158000, C331S173000, C331S17700V, C331S17700V

Reexamination Certificate

active

06943639

ABSTRACT:
A high accuracy crystal oscillator for generating a clock signal comprises a gain stage (2) controlled by a current from a current source (5), and a trimmable load capacitance (3, 4). To generate a low power clock signal, a mode control unit (7) is provided for disconnecting at least part of the load capacitance (3, 4) and activating an oscillation amplitude regulator (6) that is connected between the input terminal of the gain stage (2) and the current source (5) to reduce the current to the gain stage (2) to such a value that oscillation is maintained with a minimum amplitude.

REFERENCES:
patent: 4782309 (1988-11-01), Benjaminson
patent: 6052036 (2000-04-01), Enstrom et al.
patent: 09-102714 (1997-04-01), None
patent: 2000-010651 (2000-01-01), None
patent: 2002-091606 (2002-03-01), None

Affiliated with

Also associated with

Rating

Arrangement for low power clock generation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Arrangement for low power clock generation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arrangement for low power clock generation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3422397